Reconfigurable Computing. On-line communication strategies. Chapter 7

Transcription

1 On-line communication strategies Chapter 7 Prof. Dr.-Ing. Jürgen Teich Lehrstuhl für Hardware-Software-Co-Design

2 On-line connection - Motivation Routing-conscious temporal placement algorithms consider distance among components during placement However, they do not consider implementation of a dynamic connection mechanism required for communication among components. In this section, we will investigate existing approaches for solving the communication problem between components dynamically placed on and removed from the device, namely: Bus-based approaches Circuit routing Network-on-Chip (NoC) approaches 2

3 BUS-based communication

4 BUS - oriented communication Many components connected at fixed locations One arbiter for BUS-Management SoC (System on Chip): Buses can be used to connect different modules ARM AMBA Advance high-performance bus (AHB) Advance peripheral bus (APB) Advanced extensible Interface (AXI) IBM CoreConnect Processor local bus (PLB) On-chip peripheral bus (OPB) Silicore Wishbone Mod4 Mod 1 Arbiter Mod3 Mod2 4

5 Module 0 Module 1 Module 2 Module 3 Module 4 BUS - oriented communication Using standard bus-arbiter (Becker) OS-frame Device is divided into slots ICAP Each task must be placed in a slot Each component implements the bus-transaction Each component can be a master Mod Com Mod Com Mod Com Mod Com Bus-Macro Mod Com Source: ITIV, Karlsruhe Institute of Technology Decompessor Quelle: ITIV, Uni Karlsruhe (TH) Control Controller Com An arbiter manages the busassignment Master- Module 5

6 Communication via the OS Encapsulating the BUS-transaction in a wrapper (Platzner, Walder) Divide the device into slots OS-frame Each task must be placed in a given slot A slot is enveloped in a wrapper which hides the bus-transaction process Communication takes place through a fixed module called the OS. Each module can send a message by writing in its send buffer The OS copies messages from the send buffers to the receive buffers of modules The receive modules read their message from its receive buffer Inter Frame Communication Channels (IFCC) taskslot taskslot taskslot taskslot Adapted from: Walder, H. and Platzner, M., Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. International Conference on Engineering of Reconfigurable Systems and Algorithms, CSREA Press,

7 Communication via the OS Communication with off-chip module is also done via the OS OS-frame Adapted from: Walder, H. et al: XF-Board: Prototype Platform for Reconfigurable Hardware Operating System. In: International Conference on Engineering of Reconfigurable Systems and Architectures (ERSA),

8 ReCoBus Communication Base concept of a bus for reconfigurable systems Module 0 data out en 0 data in... Module N data out en N data in Module 0 data out data in... Module N data out data in Module 0 data en 0 out data in... Module N data en N out data in en mux tristate multiplexer logik Distributed read multiplexer chain Module 0 en data 0 out data in Module 1 en data 1 out data in... 8 Module N en data N out data in LUT LUT LUT... '0' Uniform routing Identical logic within all slots of the bus module relocation Images adapted from: D. Koch, Partial Reconfiguration on FPGAs: Architecture, Tools and Applications, Springer, D. Koch et al., Efficient Reconfigurable On-Chip Buses for FPGAs. International Symposium on Field-Programmable Custom Computing Machines, 2008.

9 ReCoBus Communication Problem: the structure of a distributed read multiplexer chain is unlikely for very fine-grained resource slot layouts: reconfigurable area Slot 1 Slot 2 Slot 3 '0' D 7..0 D D '0' '0' '0' D Adapted from: Koch, D. Partial Reconfiguration on FPGAs: Architecture, Tools and Applications, Springer, 2013 Logic overhead: 4/24 = 17% 9

10 ReCoBus Communication Problem: the structure of a distributed read multiplexer chain is unlikely for very fine-grained resource slot layouts: reconfigurable area Slot Slot 1 1 Slot 2 Slot 2 Slot 3 Slot Slot 3 4 '0' D 7..0 D D '0' '0' '0' D Logic overhead: 4/18 = 22% 10

11 ReCoBus Communication Problem: the structure of a distributed read multiplexer chain is unlikely for very fine-grained resource slot layouts: reconfigurable area Slot Slot 1 1 Slot 2 Slot Slot 2 3 Slot Slot 4 3 Slot 5 Slot Slot 4 6 '0' D 7..0 D D '0' '0' '0' D Logic overhead: 4/12 = 33% 11

12 ReCoBus Communication Problem: the structure of a distributed read multiplexer chain is unlikely for very fine-grained resource slot layouts: reconfigurable area S1 Slot S2 1 S3 Slot S4 2 S5 Slot S6 3 S7 Slot S8 4 S9Slot S10 5 S11 Slot S12 6 '0' D 7..0 D D '0' '0' '0' D Logic overhead: 4/6 = 66%; very high latency! 12

13 ReCoBus Communication Bus.de Solution: multiple independent interleaved read multiplexer chains reconfigurable area S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 D D 7..0 D D '0' Logic overhead: 1/6 = 17%; low latency and fine granularity! 13

14 ReCoBus Communication Bus.de Example system: Module 0 Module 1 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 CPU en d out en d out en d out en d out en d out en d out static system Fine slot grid for reducing internal fragmentation Alignment-multiplexer allows free module placement Interface grows together with the module complexity (size) Very low logic overhead (no extra connection logic within the slots) Allows high speed / high throughput Hot-swap module exchange runtime reconfigurable system Images adapted from: D. Koch, Partial Reconfiguration on FPGAs: Architecture, Tools and Applications, Springer, D. Koch et al., Efficient Reconfigurable On-Chip Buses for FPGAs. International Symposium on Field-Programmable Custom Computing Machines,

15 Circuit switching

16 Dynamic Networks circuit routing Architecture: Set of Processing elements Communication signals are set between two PEs using a set of switches on a path from the source to the destination Advantage: Direct communication. No need to process packets Drawbacks: Computing a route is expensive. Difficult to be done on-line Routed lines create a large amount of prohibited area Prohibited area can be overcome by using an extra layer exclusively for circuit routing Prohibited area Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices. International Conference on Field Programmable Logic and Applications, pp ,

17 The reconfigurable multiple bus (RMB) approach A set of n processing elements and k segmented buses Crosspoints (switches) are used to set the connection between the segments at run-time Switches PE 1 PE 2 PE 3 PE 4 PE 5 17

18 The reconfigurable multiple bus (RMB) approach The sender always initiates a communication request and terminates (frees) an established communication path OS-frame Each communication path is granted until the end of the communication PE 1 PE 2 PE 3 PE 4 PE 5 18

19 The reconfigurable multiple bus (RMB) approach On a columnwise reconfigurable device, the RMB provides a modular communication infrastructure OS-frame All the switches in one column are grouped together The separation of horizontal reconfigurable regions is done via bus macros Bus macros PE 1 PE 2 PE 3 PE 4 PE 5 19

20 Example: Video game Pong Source: Atari Pong arcade 20

21 Video game: Module Relocation User Input 4 Source: Atari Pong arcade Racket Position 20 Ball Position Visualization 22

22 Algorithms for Reconfiguration T 1 T 2 T 1 M 1 1 T 3 T 1 T 2 T 4 T 5 M 1 1 T 6 T 3 M 1 1 T 7 M 1 1 T 8 T 9 23

23 Algorithms for Reconfiguration TM 1 TM 2 M 3 T 3 FPGA RMB 24

24 Algorithms for Reconfiguration FPGA M1 M2 M3 RMB 25

25 Algorithms for Reconfiguration FPGA M1 M2 M3 RMB 26

26 Algorithms for Reconfiguration FPGA M1 M2 M3 RMB 27

27 Algorithms for Reconfiguration FPGA M1 M3 M2 RMB 28

28 Algorithms for Reconfiguration FPGA Minimum Bandwidth (MBW) min M1 M2 max FPGA i M3 j i, j E Minimum Cutwidth Linear Arrangement (MCLA) M2 M1 M3 FPGA RMB min max k, i, j E i k j 1, n min RMB M2 Optimal Linear M1 M3 Arrangement (OLA) i, j E i j RMB 29

29 Algorithms for Reconfiguration FPGA M1 M3 M2 RMB 30

30 Visualization Ball Position Racket Position Racket Position User Input Ball Position Visualization User Input Video game: Module Relocation CP CP CP CP User Input CP 4 58 parallel segments CP Racket Position 20 Ball Position CP Visualization 31 CP

31 Racket Position User Input Ball Position Visualization Video game: Module Relocation CP CP CP CP Task: Place modules such that for given maximal 58 parallel number segments of parallel bus segments the length of the longest connection distance is minimized length of longest connection 3 Solution: Integer Linear Program (FPL 06) 32

32 Racket Position User Input Ball Position Visualization Video game: Module Relocation CP CP CP CP length of longest connection 2 33

33 User Input Racket Position Ball Position Visualization Video game: Module Relocation CP CP CP CP length of longest connection 2 34

34 Erlangen Slot Machine Source: C. Bobda et al., The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms, In Proceedings of the IEEE International Conference on Field-Programmable Technology, pp , March 12-15,

35 Video game: Erlangen Slot Machine (ESM) Source: M. Majer et al., Erlangen Slot Machine: A dynamically reconfigurable FPGA-based computer, Journal of VLSI Signal Processing Systems, vol. 47, pp , Apr

36 Implementation Racket Position User Input Ball Position Display CP0 CP1 CP2 CP3 Source: Image obtained from Xilinx ISE 37

37 I/O Bars for Point-to-Point Links Crosspoints are typically adjusted only at a configuration process Horizontal routing track(s) within the reconfigurable area Connections are set by modifying a switch matrix configuration static system Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 bypass video out video in audio out ReCoBus audio in static system 38

38 I/O Bars for Point-to-Point Links Read-modify-write connection (up- and downstream in the same slot) Ideal for data streaming I/O bars can be segmented into multiple point-to-point links static system Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 video out video in audio out ReCoBus audio in static system 39

39 I/O Bars for Point-to-Point Links Bus.de I/O bar implementation (low logic overhead only in connection points) Modulslot mit I/O-Bar Anbindung Modulslot ohne I/O-Bar Anbindung Incoming signals Outgoing signals I/O-Bar endet in Flip-Flop I/O-Bar wird fortgesetzt Adapted from: D. Koch, Partial Reconfiguration on FPGAs: Architecture, Tools and Applications, Springer, Route through signals I/O-Bar wird ohne Unterbrechung fortgesetzt

40 Packet-based communication

41 NoC (Network on Chip) based communication A Network on Chip consists of NoC A set of processing elements A set of network elements also called routers Each PE is connected to a network element Each PE is assigned to the same address as its corresponding network element Communication is packet-based Router Each packet contains the destination address and some data Routers are used to forward packets in the right direction according to the destination address A router contains little logic. It may have some buffer for storage of packets in case of high traffic Source: S. Kumar et al., A network on chip architecture and design methodology, IEEE Annual Symposium on VLSI,

42 Dynamic Networks Limitations of fixed NoC communication Fixed position for modules Larger modules must be split Packet based communication inside a component is not efficient Direct communication must be used on a module boundary We seek a network infrastructure which allows modules placed at a given location to use all the resources in their area changes according to the placement of modules on the device Each component always accesses other components and pins for communication 43

43 Dynamic Networks DyNoC (Dynamic NoC) Architecture: like NoC architecture Set of Processing elements Set of network elements implementing routers in their basic configuration Each PE is connected to a network element Direct communication among neighbour PEs Communication is packet-based Each packet contains the destination address and some data The ratio router size/module size must be kept small Source: A. Ahmadinia et al., Online placement for dynamically reconfigurable devices. International Journal of Embedded Systems, vol. 1, no. 3/4, pp ,

44 Dynamic Networks DyNoC Dynamics in the NoC Each module is represented as a rectangular box encapsulating a given function All resources (routers and PEs) in a placement area of a module are assigned to the module Therefore, the network logic should be flexible to be used as logic in a given module Upon completion, each module restores its routers to their basic configuration Up to a selected router, all the routers in the area of a component are no more accessible from the network Each placed component accesses the network using the router attached to it North-East (NE) PE Network varies with temporal placement of modules on the device Source: A. Ahmadinia et al., Online placement for dynamically reconfigurable devices. International Journal of Embedded Systems, vol. 1, no. 3/4, pp ,

45 Dynamic Networks DyNoC - Reachability Module and pin reachability: A module (pin) is reachable iff all the messages sent to this module (pin) can reach their destination. We define the component graph G = (V,E) as follows: V is the set of components and pins An edge (u,v) belongs to E iff a path exists between u an v If G is connected, then all components and pins are reachable This increases the architectural requirements Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conference on Field Programmable Logic and Applications, pp ,

46 Dynamic Networks DyNoC - Reachability Additional architectural requirements A ring of network elements must be available around the chip The PEs at the chip boundary must be connected to the router at the chip boundary Each placed component accesses the network using the PE associated to it North-East (NE) PE Only PEs are allowed to be at the boundary of a component Source: A. Ahmadinia et al., Online placement for dynamically reconfigurable devices. International Journal of Embedded Systems, vol. 1, no. 3/4, pp ,

47 Dynamic Networks DyNoC Reachability Theorem (C. Bobda et al.): If each component is synthesized in such a way that it is internally surrounded only by processing elements, then each placement on the reconfigurable device causes a strongly connected component graph. Proof: Assume that the corresponding component graph is not strongly connected, then at least two components abut or one component abuts the device boundary. Consider, for example, case 1): Either the two components must overlap Or, one component uses some routers on its boundary. X X X PE PE PE X PE PE PE PE PE PE X Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conference on Field Programmable Logic and Applications, pp , PE PE PE PE PE PE X PE PE PE PE PE PE A X X X PE PE PE A 48

48 Dynamic Networks DyNoC Reachability Example of a feasible placement Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conference on Field Programmable Logic and Applications, pp ,

49 Dynamic Networks DyNoC Routing Routing in a mesh without obstacles The XY-router Fast and Efficient Local decisive 5 inputs and 5 outputs channels Input-FIFO on each channel The router compares its address to the destination address of a packet If X-router < X-packet, packet is sent east If X-router > X-packet, packet is sent west If X-router = X-packet and Y-router < Y-packet, packet is sent north If X-router = X-packet and Y-router > Y-packet, packet is sent south If X-router = X-packet and Y-router = Y-packet, copy packet to local FIFO y x Source: C. Bobda, Introduction to Reconfigurable Computing, Springer,

50 Dynamic Networks DyNoC Routing The dynamic placement of components creates obstacles in the network Obstacles The routing must be able to recognize obstacles and be able to surround components. Vertical and horizontal obstacles are treated differently Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conference on Field Programmable Logic and Applications, pp ,

51 Dynamic Networks DyNoC Routing S-XY Dealing with obstacles XY-Router Additionally: Activate signal to neighbours If the router is available, this control signal is high. Otherwise, it is low Component surrounding strategies are required The S-XY (Surround XY) router Operates in three modes The N-XY: Normal operating mode. The packets are routed according to the XY strategy The SH-XY: The router enters this mode when a horizontal obstacle is found The SV-XY: The router enters this mode when a vertical obstacle is found Source: C. Bobda, Introduction to Reconfigurable Computing, Springer,

52 Dynamic Networks DyNoC Routing S-XY The SH-XY mode: Surrounding obstacles in the horizontal direction Y Dest > Y Router Routing Path 1 X Dest < X Router Dest Obstacle Component X Dest = X Router Y Dest < Y Router X Dest = X Router Routing Path 2 Y Dest = Y Router Stamp packets to avoid ping-pong game Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conference on Field Programmable Logic and Applications, pp ,

53 Dynamic Networks DyNoC Routing S-XY Surrounding obstacles in the vertical direction Place a stamp on packets to avoid a ping pong game Ping pong game Routing Path1 Obstacle Component Routing Path2 Destination Component Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conference on Field Programmable Logic and Applications, pp ,

54 Implementation Virtex II x4 DyNoC 7% of FPGA-Usage Router latency: 2,5ns 32bit Data-BUS and 6x4x32bit FIFO per Router Source: C. Bobda et al., A Dynamic NoC Approach for Communication in Reconfigurable Devices, International Conference on Field Programmable Logic and Applications, pp ,

55 Dynamic Networks DyNoC Routing S-XY Theorem (C. Bobda et al.): The S-XY algorithm is deadlockfree, i.e., each packet will reach its destination after a finite number of steps. Proof: Exercise Prove that Each component is reachable, i.e., a path is always available from source to destination A packet is never blocked in the network (Theorem 1) Since a packet can never be blocked, this will happen only if a packet is looping around a component. Prove that this will never happen! Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conference on Field Programmable Logic and Applications, pp ,

56 C4 C 3 Dynamic Networks DyNoC Routing S-XY The decision to left/right or up/down is taken arbitrarily In the worst case, the path can be very long To avoid this, consider guiding the router by the components D C2 C S Guided routing Source: C. Bobda et al., DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices, International Conference on Field Programmable Logic and Applications, pp ,