DSENT A Tool Connecting Emerging Photonics with Electronics for Opto- Electronic Networks-on-Chip Modeling Chen Sun

Size: px
Start display at page:

Download "DSENT A Tool Connecting Emerging Photonics with Electronics for Opto- Electronic Networks-on-Chip Modeling Chen Sun"

Transcription

1 A Tool Connecting Emerging Photonics with Electronics for Opto- Electronic Networks-on-Chip Modeling Chen Sun In collaboration with: Chia-Hsin Owen Chen George Kurian Lan Wei Jason Miller Jurgen Michel Dimitri Antoniadis Lionel Kimerling Anant Agarwal Li-Shiuan Peh Vladimir Stojanovic MIT Microphotonics Center Fall 2012 Meeting 10/15/2012 1

2 Multi-Core Connectivity Challenge Every choice has a cost! 10/15/2012 2

3 Huge Potential for Photonics Photonics can tackle the multi-core connectivity problem Photonics core-to-core [Vantrease 08, Kurian 10] Photonics core-to-dram [Beamer 10, Udipi 11] Photonics-inspired architectures can improve performance over fully-electrical designs Device assumptions vary wildly from work to work Architectures presented in a 1-D fashion: No clear way for device/circuit designers to get feedback on their devices 10/15/2012 3

4 What is? Design Space Exploration of Networks Tool Software developed for power/area evaluation of interconnection networks Network Description Core Network Models Network Components Library Network Cost Metrics Technology Primitives Library Technology Parameters Technology Characterization Explore impact of photonics in the context of a bigger system 10/15/2012 4

5 as a Modeling Tool A cost evaluator, NOT a performance simulator A just give me a reasonable number mode Assumes some reasonable network activity Outputs network metrics like power, area, energy/bit, etc. Designed for easy integration with performance simulators that exist Technology Parameters Network Activity (optional) Technology node, optical parameters, etc. User input or from a performance simulator Network Power Network Network parameters, architecture Network Area 10/15/2012 5

6 Modeling Electronics Most of the network is routers and electrical links Rigorous electrical models in an ASIC-driven approach Models hierarchically made from basic technology parameters Technology Characterization Leakages Currents Capacitances Components Library Mesh Network Network Models Constructs Used in Technology Primitives Library Standard Cells Custom Cells Used in Delay/Timing Model Transition Density Model 10/15/2012 6

7 PAR PAR PAR PAR PAR PAR PAR Power (mw) PAR PAR PAR PAR PAR PAR Validating Electrical Models Default Parameters: 5x5 Mesh Router 2 Virtual Channels 64b Flit Width Vary # Bufs Vary # VCs Vary # Ports Vary Flit Width (bit) Input Buffer (Dynamic) Input Buffer (Leakage) Crossbar (Dynamic) Crossbar (Leakage) SA (Dynamic) SA (Leakage) Other (Dynamic) Other (Leakage) Power estimate within 20% of placed and routed router designs Accurate across a wide range of designs Successor to Orion 2.0 [Kahng, DATE 2009] for on-chip network cost modeling 10/15/2012 7

8 Modeling Photonics in Receivers/Modulator driver circuits optimization Based on previous work in [Georgas, CICC 2011] Backend circuitry leverages electrical framework Thermal tuning backend Serializers/Deserializers Clocking 10/15/2012 8

9 Link Optimization Example Designing a 128 Gb/s WDM link Data-rate is a degree of freedom 4 32 Gb/s, or 64 2 Gb/s Thermal tuning, SerDes, laser power are modeled 10/15/2012 9

10 Photonics Integration in Optical link, circuit, device models Based on previous work in [Georgas, CICC 2011] Plugs seamlessly into evaluation interface Enables evaluations of Electro-Optic Networks Technology Characterization Losses Laser Efficiency Electronic Components Routers Used in Network Models Constructs Technology Primitives Library Modulators Receivers Used in Optical Components Used in 10/15/

11 Applying to a Full System ATAC+ Architecture Appears in [Kurian, IPDPS 2012] 1024 Cores Divided into 64 optically connected clusters 16 electrically-connected cores per cluster, with an I/O optical hub Optical ring bus overlaid on top of an electrical mesh Supports efficient low-latency broadcasts Representative of how people think optics will be used in an on-chip system models the full network Performance simulation done using Graphite [Miller, HPCA 2010] 11

12 Bad Energy (?) Energy = Total energy consumed over the course of the application Averaged across all benchmark applications EMesh-Bcast electrical mesh network with optimized broadcast support ATAC+ network uses more energy to finish a benchmark Though with 30% average lower runtime than the best fully electrical network Ring tuning and laser power are significant 12

13 Why are Laser and Tuning Bad? Static vs dynamic power Non-data-dependent (NDD) vs data-dependent (DD) power Leakage and ungated clocks are NDD Transistor switching is DD Off-chip laser, cannot be throttled quickly, NDD thermal tuning, cannot tune rings in and out quickly, NDD Network Peak Saturation Throughput = 0.15 flits/cycle/core Network sized to handle peak throughput Average utilization <20% 80% of the network is idle! Benchmark Applications 10/15/

14 Energy (Normalized) Energy (Normalized) Wish List Item #1: Throttled Lasers Laser Other Laser Other Standard Laser Throttled Laser Idle and unicast modes through laser throttling Without throttling, laser must be at full broadcast-capable strength all the time Laser energy drops to 2% of total (cache + network) Throttle-able on-chip lasers are extremely valuable 14

15 Energy (Normalized) Energy (Normalized) Wish List Item #2: No Ring Tuning Laser Ring Tuning Other Laser Other Thermally Tuned Athermal Rings Thermal tuning 35% of total energy Athermal rings that do not require thermal tuning are extremely important 15

16 Comparing Energy ATAC+ (Cons) Standard laser Needs tuning ATAC+ Throttled Laser, Athermal rings ATAC+ (Ideal) 100% efficient laser lossless devices Significant energy savings if wish-list items are available Wishlist ATAC+ achieves energy efficiency that is close to the ideal Using E-D product metric, ATAC+ wins by >80% 16

17 Conclusion We created to bridge photonics and electronics Generalized methodology for digital components Allows architectural explorations of photonic interconnects We showed a -enabled study of a representative photonic network architecture Problem of non-data-dependent laser and thermal tuning power due to low average utilizations Identified throttle-able on-chip lasers and athermal ring resonators as key for energy-efficient photonics Website (With Download Link): 10/15/

18 Backups 10/15/

19 Framework After initial modeling of implementation, design can be optimized and evaluated 10/15/2012 [Georgas, CICC 2011] 19

20 Effect of Utilization Non-data-dependent energy dominant Low Throughput Data-Dependent energy dominant Max Throughput 10/15/

21 Evaluation Infrastructure Cache Models Core Models Benchmark Network Models Inputs Cache & Directory Counters Electrical Technology Parameters Graphite NM Optical Link Counters Electrical Router & Link Counters Optical Technology Parameters McPAT Tools Completion Time Cache Energy & Area Electrical Router & Link Energy & Area Optical Link Energy & Area 10/15/ Outputs

22 Great Performance! Benchmarks ATAC+ demonstrates significant performance advantage 40% over broadcast-assisted electrical baseline (EMesh-Bcast) 130% over standard electrical baseline (EMesh-Pure) EMesh-BCast and EMesh-Pure differ according to the frequency of read-write sharing 22

23 Comparing E-D Product ATAC+(Ideal) ATAC+ ATAC+(ThrottledOnly) ATAC+(Cons) EMesh-BCast EMesh-Pure ATAC+(Cons) = Throttled laser, Needs tuning ATAC+(ThrottleOnly) = Throttled laser, Needs tuning ATAC+ = Throttled Laser, Athermal rings ATAC+(Ideal) = 100% efficient laser, lossless devices With the wishlist items, ATAC+ achieves % improvement over best electrical baseline (EMesh-BCast) Even ATAC+(Cons) can win over best electrical baseline in some benchmarks 23

24 Energy (Normalized) Core NDD Energy Depends On Network Performance Core DD Core NDD Caches Network ATAC+ EMesh -BCast 0 radix fmm ocean ocean average contig non-contig Higher performance network with higher energy may give better system energy benefits Correct trade-off only apparent with a full-system evaluation 24

25 Energy (Normalized) Energy (Normalized) System Energy Shows Different Trends Than Network Energy ATAC+ conservative variants worse ATAC+ conservative variants better Network Network Caches Core NETWORK SYSTEM 25

26 Technology Sensitivity Tuned Rings, Standard Laser, 30% Laser Efficiency, 0.2 db Waveguide Loss ATAC+ (Cons) 100% Laser Efficiency, 0dB Waveguide Loss ATAC+ (Ideal) ATAC+ (ThrottledOnly) ATAC+ Laser Throttling Athermal Rings 26

Monolithic Integration of Energy-efficient CMOS Silicon Photonic Interconnects

Monolithic Integration of Energy-efficient CMOS Silicon Photonic Interconnects Monolithic Integration of Energy-efficient CMOS Silicon Photonic Interconnects Vladimir Stojanović Integrated Systems Group Massachusetts Institute of Technology Manycore SOC roadmap fuels bandwidth demand

More information

Brief Background in Fiber Optics

Brief Background in Fiber Optics The Future of Photonics in Upcoming Processors ECE 4750 Fall 08 Brief Background in Fiber Optics Light can travel down an optical fiber if it is completely confined Determined by Snells Law Various modes

More information

Low-Power Interconnection Networks

Low-Power Interconnection Networks Low-Power Interconnection Networks Li-Shiuan Peh Associate Professor EECS, CSAIL & MTL MIT 1 Moore s Law: Double the number of transistors on chip every 2 years 1970: Clock speed: 108kHz No. transistors:

More information

ATAC: Improving Performance and Programmability with On-Chip Optical Networks

ATAC: Improving Performance and Programmability with On-Chip Optical Networks ATAC: Improving Performance and Programmability with On-Chip Optical Networks James Psota, Jason Miller, George Kurian, Nathan Beckmann, Jonathan Eastep, Henry Hoffman, Jifeng Liu, Mark Beals, Jurgen Michel,

More information

Phastlane: A Rapid Transit Optical Routing Network

Phastlane: A Rapid Transit Optical Routing Network Phastlane: A Rapid Transit Optical Routing Network Mark Cianchetti, Joseph Kerekes, and David Albonesi Computer Systems Laboratory Cornell University The Interconnect Bottleneck Future processors: tens

More information

Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-Clockwise Optical Routing

Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-Clockwise Optical Routing Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-Clockwise Optical Routing Matthew Kennedy and Avinash Karanth Kodi School of Electrical Engineering and Computer Science Ohio University,

More information

SCORPIO: 36-Core Shared Memory Processor

SCORPIO: 36-Core Shared Memory Processor : 36- Shared Memory Processor Demonstrating Snoopy Coherence on a Mesh Interconnect Chia-Hsin Owen Chen Collaborators: Sunghyun Park, Suvinay Subramanian, Tushar Krishna, Bhavya Daya, Woo Cheol Kwon, Brett

More information

CMOS Photonic Processor-Memory Networks

CMOS Photonic Processor-Memory Networks CMOS Photonic Processor-Memory Networks Vladimir Stojanović Integrated Systems Group Massachusetts Institute of Technology Acknowledgments Krste Asanović, Rajeev Ram, Franz Kaertner, Judy Hoyt, Henry Smith,

More information

The Design and Implementation of a Low-Latency On-Chip Network

The Design and Implementation of a Low-Latency On-Chip Network The Design and Implementation of a Low-Latency On-Chip Network Robert Mullins 11 th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 24-27 th, 2006, Yokohama, Japan. Introduction Current

More information

ECE/CS 757: Advanced Computer Architecture II Interconnects

ECE/CS 757: Advanced Computer Architecture II Interconnects ECE/CS 757: Advanced Computer Architecture II Interconnects Instructor:Mikko H Lipasti Spring 2017 University of Wisconsin-Madison Lecture notes created by Natalie Enright Jerger Lecture Outline Introduction

More information

Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation

Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation Kshitij Bhardwaj Dept. of Computer Science Columbia University Steven M. Nowick 2016 ACM/IEEE Design Automation

More information

Network on Chip Architecture: An Overview

Network on Chip Architecture: An Overview Network on Chip Architecture: An Overview Md Shahriar Shamim & Naseef Mansoor 12/5/2014 1 Overview Introduction Multi core chip Challenges Network on Chip Architecture Regular Topology Irregular Topology

More information

Hybrid On-chip Data Networks. Gilbert Hendry Keren Bergman. Lightwave Research Lab. Columbia University

Hybrid On-chip Data Networks. Gilbert Hendry Keren Bergman. Lightwave Research Lab. Columbia University Hybrid On-chip Data Networks Gilbert Hendry Keren Bergman Lightwave Research Lab Columbia University Chip-Scale Interconnection Networks Chip multi-processors create need for high performance interconnects

More information

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Proposal for Thesis Research in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

More information

Silicon-Photonic Clos Networks for Global On-Chip Communication

Silicon-Photonic Clos Networks for Global On-Chip Communication Appears in the Proceedings of the 3rd International Symposium on Networks-on-Chip (NOCS-3), May 9 Silicon-Photonic Clos Networks for Global On-Chip Communication Ajay Joshi *, Christopher Batten *, Yong-Jin

More information

PREDICTION MODELING FOR DESIGN SPACE EXPLORATION IN OPTICAL NETWORK ON CHIP

PREDICTION MODELING FOR DESIGN SPACE EXPLORATION IN OPTICAL NETWORK ON CHIP PREDICTION MODELING FOR DESIGN SPACE EXPLORATION IN OPTICAL NETWORK ON CHIP SARA KARIMI A Thesis in The Department Of Electrical and Computer Engineering Presented in Partial Fulfillment of the Requirements

More information

OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures

OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures Md Ashif I Sikder, Avinash K Kodi, Matthew Kennedy and Savas Kaya School of Electrical Engineering and Computer Science Ohio University

More information

On-chip Monitoring Infrastructures and Strategies for Many-core Systems

On-chip Monitoring Infrastructures and Strategies for Many-core Systems On-chip Monitoring Infrastructures and Strategies for Many-core Systems ussell Tessier, Jia Zhao, Justin Lu, Sailaja Madduri, and Wayne Burleson esearch supported by the Semiconductor esearch Corporation

More information

Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers

Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers Young Hoon Kang, Taek-Jun Kwon, and Jeff Draper {youngkan, tjkwon, draper}@isi.edu University of Southern California

More information

Interconnection Networks

Interconnection Networks Lecture 18: Interconnection Networks Parallel Computer Architecture and Programming CMU 15-418/15-618, Spring 2015 Credit: many of these slides were created by Michael Papamichael This lecture is partially

More information

Design of Adaptive Communication Channel Buffers for Low-Power Area- Efficient Network-on. on-chip Architecture

Design of Adaptive Communication Channel Buffers for Low-Power Area- Efficient Network-on. on-chip Architecture Design of Adaptive Communication Channel Buffers for Low-Power Area- Efficient Network-on on-chip Architecture Avinash Kodi, Ashwini Sarathy * and Ahmed Louri * Department of Electrical Engineering and

More information

Interconnection Networks

Interconnection Networks Lecture 17: Interconnection Networks Parallel Computer Architecture and Programming A comment on web site comments It is okay to make a comment on a slide/topic that has already been commented on. In fact

More information

Silicon-Photonic Clos Networks for Global On-Chip Communication

Silicon-Photonic Clos Networks for Global On-Chip Communication Silicon-Photonic Clos Networks for Global On-Chip Communication Ajay Joshi *, Christopher Batten *, Yong-Jin Kwon, Scott Beamer, Imran Shamim * Krste Asanović, Vladimir Stojanović * * Department of EECS,

More information

ECE 551 System on Chip Design

ECE 551 System on Chip Design ECE 551 System on Chip Design Introducing Bus Communications Garrett S. Rose Fall 2018 Emerging Applications Requirements Data Flow vs. Processing µp µp Mem Bus DRAMC Core 2 Core N Main Bus µp Core 1 SoCs

More information

Meet in the Middle: Leveraging Optical Interconnection Opportunities in Chip Multi Processors

Meet in the Middle: Leveraging Optical Interconnection Opportunities in Chip Multi Processors Meet in the Middle: Leveraging Optical Interconnection Opportunities in Chip Multi Processors Sandro Bartolini* Department of Information Engineering, University of Siena, Italy bartolini@dii.unisi.it

More information

Networks for Multi-core Chips A A Contrarian View. Shekhar Borkar Aug 27, 2007 Intel Corp.

Networks for Multi-core Chips A A Contrarian View. Shekhar Borkar Aug 27, 2007 Intel Corp. Networks for Multi-core hips A A ontrarian View Shekhar Borkar Aug 27, 2007 Intel orp. 1 Outline Multi-core system outlook On die network challenges A simple contrarian proposal Benefits Summary 2 A Sample

More information

EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 12: On-Chip Interconnects

EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 12: On-Chip Interconnects 1 EECS 598: Integrating Emerging Technologies with Computer Architecture Lecture 12: On-Chip Interconnects Instructor: Ron Dreslinski Winter 216 1 1 Announcements Upcoming lecture schedule Today: On-chip

More information

Quality-of-Service for a High-Radix Switch

Quality-of-Service for a High-Radix Switch Quality-of-Service for a High-Radix Switch Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David Blaauw, Ronald G. Dreslinski, Reetuparna Das, and Trevor Mudge University of Michigan 51 st DAC 06/05/2014

More information

Index 283. F Fault model, 121 FDMA. See Frequency-division multipleaccess

Index 283. F Fault model, 121 FDMA. See Frequency-division multipleaccess Index A Active buffer window (ABW), 34 35, 37, 39, 40 Adaptive data compression, 151 172 Adaptive routing, 26, 100, 114, 116 119, 121 123, 126 128, 135 137, 139, 144, 146, 158 Adaptive voltage scaling,

More information

Lecture 3: Topology - II

Lecture 3: Topology - II ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 3: Topology - II Tushar Krishna Assistant Professor School of Electrical and

More information

Analyzing the Effectiveness of On-chip Photonic Interconnects with a Hybrid Photo-electrical Topology

Analyzing the Effectiveness of On-chip Photonic Interconnects with a Hybrid Photo-electrical Topology Analyzing the Effectiveness of On-chip Photonic Interconnects with a Hybrid Photo-electrical Topology Yong-jin Kwon Department of EECS, University of California, Berkeley, CA Abstract To improve performance

More information

Thomas Moscibroda Microsoft Research. Onur Mutlu CMU

Thomas Moscibroda Microsoft Research. Onur Mutlu CMU Thomas Moscibroda Microsoft Research Onur Mutlu CMU CPU+L1 CPU+L1 CPU+L1 CPU+L1 Multi-core Chip Cache -Bank Cache -Bank Cache -Bank Cache -Bank CPU+L1 CPU+L1 CPU+L1 CPU+L1 Accelerator, etc Cache -Bank

More information

Lecture 22: Router Design

Lecture 22: Router Design Lecture 22: Router Design Papers: Power-Driven Design of Router Microarchitectures in On-Chip Networks, MICRO 03, Princeton A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip

More information

Interconnection Networks: Topology. Prof. Natalie Enright Jerger

Interconnection Networks: Topology. Prof. Natalie Enright Jerger Interconnection Networks: Topology Prof. Natalie Enright Jerger Topology Overview Definition: determines arrangement of channels and nodes in network Analogous to road map Often first step in network design

More information

Future of Interconnect Fabric A Contrarian View. Shekhar Borkar June 13, 2010 Intel Corp. 1

Future of Interconnect Fabric A Contrarian View. Shekhar Borkar June 13, 2010 Intel Corp. 1 Future of Interconnect Fabric A ontrarian View Shekhar Borkar June 13, 2010 Intel orp. 1 Outline Evolution of interconnect fabric On die network challenges Some simple contrarian proposals Evaluation and

More information

Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics

Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics Scott Beamer, Chen Sun, Yong-Jin Kwon Ajay Joshi, Christopher Batten, Vladimir Stojanović, Krste Asanović Dept. of EECS

More information

EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 14: Photonic Interconnect

EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 14: Photonic Interconnect 1 EECS 598: Integrating Emerging Technologies with Computer Architecture Lecture 14: Photonic Interconnect Instructor: Ron Dreslinski Winter 2016 1 1 Announcements 2 Remaining lecture schedule 3/15: Photonics

More information

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow Abstract: High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture

More information

FUTURE high-performance computers (HPCs) and data. Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture

FUTURE high-performance computers (HPCs) and data. Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture Chao Chen, Student Member, IEEE, and Ajay Joshi, Member, IEEE (Invited Paper) Abstract Silicon-photonic links have been proposed

More information

Designing Low-power, Low-latency Networks-on-chip by Optimally Combining Electrical and Optical Links

Designing Low-power, Low-latency Networks-on-chip by Optimally Combining Electrical and Optical Links Designing Low-power, Low-latency Networks-on-chip by Optimally Combining Electrical and Optical Links Sebastian Werner, Javier Navaridas and Mikel Luján The University of Manchester, Manchester, M13 9PL,

More information

Scaling routers: Where do we go from here?

Scaling routers: Where do we go from here? Scaling routers: Where do we go from here? HPSR, Kobe, Japan May 28 th, 2002 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University nickm@stanford.edu www.stanford.edu/~nickm

More information

A Survey of Techniques for Power Aware On-Chip Networks.

A Survey of Techniques for Power Aware On-Chip Networks. A Survey of Techniques for Power Aware On-Chip Networks. Samir Chopra Ji Young Park May 2, 2005 1. Introduction On-chip networks have been proposed as a solution for challenges from process technology

More information

IITD OPTICAL STACK : LAYERED ARCHITECTURE FOR PHOTONIC INTERCONNECTS

IITD OPTICAL STACK : LAYERED ARCHITECTURE FOR PHOTONIC INTERCONNECTS SRISHTI PHOTONICS RESEARCH GROUP INDIAN INSTITUTE OF TECHNOLOGY, DELHI 1 IITD OPTICAL STACK : LAYERED ARCHITECTURE FOR PHOTONIC INTERCONNECTS Authors: Janib ul Bashir and Smruti R. Sarangi Indian Institute

More information

Centip3De: A 64-Core, 3D Stacked, Near-Threshold System

Centip3De: A 64-Core, 3D Stacked, Near-Threshold System 1 1 1 Centip3De: A 64-Core, 3D Stacked, Near-Threshold System Ronald G. Dreslinski David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman

More information

A Case for Fine-Grain Adaptive Cache Coherence George Kurian, Omer Khan, and Srinivas Devadas

A Case for Fine-Grain Adaptive Cache Coherence George Kurian, Omer Khan, and Srinivas Devadas Computer Science and Artificial Intelligence Laboratory Technical Report MIT-CSAIL-TR-2012-012 May 22, 2012 A Case for Fine-Grain Adaptive Cache Coherence George Kurian, Omer Khan, and Srinivas Devadas

More information

Designing 3D Tree-based FPGA TSV Count Minimization. V. Pangracious, Z. Marrakchi, H. Mehrez UPMC Sorbonne University Paris VI, France

Designing 3D Tree-based FPGA TSV Count Minimization. V. Pangracious, Z. Marrakchi, H. Mehrez UPMC Sorbonne University Paris VI, France Designing 3D Tree-based FPGA TSV Count Minimization V. Pangracious, Z. Marrakchi, H. Mehrez UPMC Sorbonne University Paris VI, France 13 avril 2013 Presentation Outlook Introduction : 3D Tree-based FPGA

More information

Challenges for Future Interconnection Networks Hot Interconnects Panel August 24, Dennis Abts Sr. Principal Engineer

Challenges for Future Interconnection Networks Hot Interconnects Panel August 24, Dennis Abts Sr. Principal Engineer Challenges for Future Interconnection Networks Hot Interconnects Panel August 24, 2006 Sr. Principal Engineer Panel Questions How do we build scalable networks that balance power, reliability and performance

More information

Lecture 15: NoC Innovations. Today: power and performance innovations for NoCs

Lecture 15: NoC Innovations. Today: power and performance innovations for NoCs Lecture 15: NoC Innovations Today: power and performance innovations for NoCs 1 Network Power Power-Driven Design of Router Microarchitectures in On-Chip Networks, MICRO 03, Princeton Energy for a flit

More information

On-Chip Communications

On-Chip Communications On-Chip Communications Somayyeh Koohi Department of Computer Engineering Sharif University of Technology 1 Introduction Adapted with modifications from lecture notes prepared by S.Pasricha and N.Dutt Outline

More information

Transistors and Wires

Transistors and Wires Computer Architecture A Quantitative Approach, Fifth Edition Chapter 1 Fundamentals of Quantitative Design and Analysis Part II These slides are based on the slides provided by the publisher. The slides

More information

CSE 548 Computer Architecture. Clock Rate vs IPC. V. Agarwal, M. S. Hrishikesh, S. W. Kechler. D. Burger. Presented by: Ning Chen

CSE 548 Computer Architecture. Clock Rate vs IPC. V. Agarwal, M. S. Hrishikesh, S. W. Kechler. D. Burger. Presented by: Ning Chen CSE 548 Computer Architecture Clock Rate vs IPC V. Agarwal, M. S. Hrishikesh, S. W. Kechler. D. Burger Presented by: Ning Chen Transistor Changes Development of silicon fabrication technology caused transistor

More information

Network on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN

Network on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN Network on Chip Architectures BY JAGAN MURALIDHARAN NIRAJ VASUDEVAN Multi Core Chips No more single processor systems High computational power requirements Increasing clock frequency increases power dissipation

More information

OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs

OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs 4B-1 Sudeep Pasricha, Shirish Bahirat Colorado State University, Fort Collins, CO {sudeep, shirish.bahirat}@colostate.edu Abstract - Three-dimensional

More information

NetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013

NetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013 NetSpeed ORION: A New Approach to Design On-chip Interconnects August 26 th, 2013 INTERCONNECTS BECOMING INCREASINGLY IMPORTANT Growing number of IP cores Average SoCs today have 100+ IPs Mixing and matching

More information

Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems

Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems 1 Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems Ronald Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Pinckney, Geoff Blake, Michael Cieslak, Reetuparna

More information

Power Reduction Techniques in the Memory System. Typical Memory Hierarchy

Power Reduction Techniques in the Memory System. Typical Memory Hierarchy Power Reduction Techniques in the Memory System Low Power Design for SoCs ASIC Tutorial Memories.1 Typical Memory Hierarchy On-Chip Components Control edram Datapath RegFile ITLB DTLB Instr Data Cache

More information

Couture: Tailoring STT-MRAM for Persistent Main Memory. Mustafa M Shihab Jie Zhang Shuwen Gao Joseph Callenes-Sloan Myoungsoo Jung

Couture: Tailoring STT-MRAM for Persistent Main Memory. Mustafa M Shihab Jie Zhang Shuwen Gao Joseph Callenes-Sloan Myoungsoo Jung Couture: Tailoring STT-MRAM for Persistent Main Memory Mustafa M Shihab Jie Zhang Shuwen Gao Joseph Callenes-Sloan Myoungsoo Jung Executive Summary Motivation: DRAM plays an instrumental role in modern

More information

Phase Change Memory An Architecture and Systems Perspective

Phase Change Memory An Architecture and Systems Perspective Phase Change Memory An Architecture and Systems Perspective Benjamin C. Lee Stanford University bcclee@stanford.edu Fall 2010, Assistant Professor @ Duke University Benjamin C. Lee 1 Memory Scaling density,

More information

TDT Appendix E Interconnection Networks

TDT Appendix E Interconnection Networks TDT 4260 Appendix E Interconnection Networks Review Advantages of a snooping coherency protocol? Disadvantages of a snooping coherency protocol? Advantages of a directory coherency protocol? Disadvantages

More information

Designing Chip-Level Nanophotonic Interconnection Networks

Designing Chip-Level Nanophotonic Interconnection Networks IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 2, NO. 2, JUNE 2012 137 Designing Chip-Level Nanophotonic Interconnection Networks Christopher Batten, Member, IEEE, Ajay Joshi,

More information

Quest for High-Performance Bufferless NoCs with Single-Cycle Express Paths and Self-Learning Throttling

Quest for High-Performance Bufferless NoCs with Single-Cycle Express Paths and Self-Learning Throttling Quest for High-Performance Bufferless NoCs with Single-Cycle Express Paths and Self-Learning Throttling Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan Dept. of Electrical Engineering and Computer

More information

Name: ESE370 Fall 2012

Name: ESE370 Fall 2012 University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2012 Final Friday, December 14 Problem weightings

More information

Re-architecting DRAM with Monolithically Integrated Silicon Photonics

Re-architecting DRAM with Monolithically Integrated Silicon Photonics Re-architecting DRAM with Monolithically Integrated Silicon Photonics Scott Beamer Chen Sun Yong-jin Kwon Ajay Joshi Christopher Batten Vladimir Stojanovic Krste Asanovi Electrical Engineering and Computer

More information

Moving Forward with the IPI Photonics Roadmap

Moving Forward with the IPI Photonics Roadmap Moving Forward with the IPI Photonics Roadmap TWG Chairs: Rich Grzybowski, Corning (acting) Rick Clayton, Clayton Associates Integration, Packaging & Interconnection: How does the chip get to the outside

More information

Lecture 2: Topology - I

Lecture 2: Topology - I ECE 8823 A / CS 8803 - ICN Interconnection Networks Spring 2017 http://tusharkrishna.ece.gatech.edu/teaching/icn_s17/ Lecture 2: Topology - I Tushar Krishna Assistant Professor School of Electrical and

More information

Fundamentals of Quantitative Design and Analysis

Fundamentals of Quantitative Design and Analysis Fundamentals of Quantitative Design and Analysis Dr. Jiang Li Adapted from the slides provided by the authors Computer Technology Performance improvements: Improvements in semiconductor technology Feature

More information

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology 1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark Outline 2 Motivation ReNoC Basic

More information

PERFORMANCE EVALUATION OF WIRELESS NETWORKS ON CHIP JYUN-LYANG CHANG

PERFORMANCE EVALUATION OF WIRELESS NETWORKS ON CHIP JYUN-LYANG CHANG PERFORMANCE EVALUATION OF WIRELESS NETWORKS ON CHIP By JYUN-LYANG CHANG A thesis submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING WASHINGTON

More information

PSMC Roadmap For Integrated Photonics Manufacturing

PSMC Roadmap For Integrated Photonics Manufacturing PSMC Roadmap For Integrated Photonics Manufacturing Richard Otte Promex Industries Inc. Santa Clara California For the Photonics Systems Manufacturing Consortium April 21, 2016 Meeting the Grand Challenges

More information

Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public

Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary

More information

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance IEEE/ACM 45th Annual International Symposium on Microarchitecture Dynamic Reconfiguration of D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance Randy Morris, Avinash Karanth

More information

Packet Switch Architecture

Packet Switch Architecture Packet Switch Architecture 3. Output Queueing Architectures 4. Input Queueing Architectures 5. Switching Fabrics 6. Flow and Congestion Control in Sw. Fabrics 7. Output Scheduling for QoS Guarantees 8.

More information

Packet Switch Architecture

Packet Switch Architecture Packet Switch Architecture 3. Output Queueing Architectures 4. Input Queueing Architectures 5. Switching Fabrics 6. Flow and Congestion Control in Sw. Fabrics 7. Output Scheduling for QoS Guarantees 8.

More information

A Composite and Scalable Cache Coherence Protocol for Large Scale CMPs

A Composite and Scalable Cache Coherence Protocol for Large Scale CMPs A Composite and Scalable Cache Coherence Protocol for Large Scale CMPs Yi Xu, Yu Du, Youtao Zhang, Jun Yang Department of Electrical and Computer Engineering Department of Computer Science University of

More information

Exploiting Dark Silicon in Server Design. Nikos Hardavellas Northwestern University, EECS

Exploiting Dark Silicon in Server Design. Nikos Hardavellas Northwestern University, EECS Exploiting Dark Silicon in Server Design Nikos Hardavellas Northwestern University, EECS Moore s Law Is Alive And Well 90nm 90nm transistor (Intel, 2005) Swine Flu A/H1N1 (CDC) 65nm 45nm 32nm 22nm 16nm

More information

ECE 486/586. Computer Architecture. Lecture # 2

ECE 486/586. Computer Architecture. Lecture # 2 ECE 486/586 Computer Architecture Lecture # 2 Spring 2015 Portland State University Recap of Last Lecture Old view of computer architecture: Instruction Set Architecture (ISA) design Real computer architecture:

More information

NoCAlert: An On-Line and Real- Time Fault Detection Mechanism for Network-on-Chip Architectures

NoCAlert: An On-Line and Real- Time Fault Detection Mechanism for Network-on-Chip Architectures NoCAlert: An On-Line and Real- Time Fault Detection Mechanism for Network-on-Chip Architectures Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, and Yiannakis Sazeides University of Cyprus

More information

Ultra-Fast NoC Emulation on a Single FPGA

Ultra-Fast NoC Emulation on a Single FPGA The 25 th International Conference on Field-Programmable Logic and Applications (FPL 2015) September 3, 2015 Ultra-Fast NoC Emulation on a Single FPGA Thiem Van Chu, Shimpei Sato, and Kenji Kise Tokyo

More information

Rethinking Last-Level Cache Management for Multicores Operating at Near-Threshold

Rethinking Last-Level Cache Management for Multicores Operating at Near-Threshold Rethinking Last-Level Cache Management for Multicores Operating at Near-Threshold Farrukh Hijaz, Omer Khan University of Connecticut Power Efficiency Performance/Watt Multicores enable efficiency Power-performance

More information

Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni

Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni Department of Computer Science Columbia University in the City of New York NSF Workshop on Emerging Technologies

More information

Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity. Donghyuk Lee Carnegie Mellon University

Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity. Donghyuk Lee Carnegie Mellon University Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity Donghyuk Lee Carnegie Mellon University Problem: High DRAM Latency processor stalls: waiting for data main memory high latency Major bottleneck

More information

Design-Induced Latency Variation in Modern DRAM Chips:

Design-Induced Latency Variation in Modern DRAM Chips: Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms Donghyuk Lee 1,2 Samira Khan 3 Lavanya Subramanian 2 Saugata Ghose 2 Rachata Ausavarungnirun

More information

Energy-Proportional Photonic Interconnects

Energy-Proportional Photonic Interconnects Energy-Proportional Photonic Interconnects YIGIT DEMIR, Intel NIKOS HARDAVELLAS, Northwestern University Photonic interconnects have emerged as the prime candidate technology for efficient networks on

More information

EC 513 Computer Architecture

EC 513 Computer Architecture EC 513 Computer Architecture On-chip Networking Prof. Michel A. Kinsy Virtual Channel Router VC 0 Routing Computation Virtual Channel Allocator Switch Allocator Input Ports VC x VC 0 VC x It s a system

More information

Lecture: Memory, Multiprocessors. Topics: wrap-up of memory systems, intro to multiprocessors and multi-threaded programming models

Lecture: Memory, Multiprocessors. Topics: wrap-up of memory systems, intro to multiprocessors and multi-threaded programming models Lecture: Memory, Multiprocessors Topics: wrap-up of memory systems, intro to multiprocessors and multi-threaded programming models 1 Refresh Every DRAM cell must be refreshed within a 64 ms window A row

More information

RADEON X1000 Memory Controller

RADEON X1000 Memory Controller RADEON X1000 Memory Controller Ring Bus Memory Controller Supports today s fastest graphics memory devices GDDR3, 48+ GB/sec 512-bit Ring Bus Simplifies layout and enables extreme memory clock scaling

More information

A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports

A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports Takeshi Shimizu, Yukihiro Nakagawa, Sridhar Pathi, Yasushi Umezawa, Takashi Miyoshi, Yoichi Koyanagi, Takeshi Horie, Akira Hattori Hot

More information

Chapter 2: Computer-System Structures. Hmm this looks like a Computer System?

Chapter 2: Computer-System Structures. Hmm this looks like a Computer System? Chapter 2: Computer-System Structures Lab 1 is available online Last lecture: why study operating systems? Purpose of this lecture: general knowledge of the structure of a computer system and understanding

More information

PicoServer : Using 3D Stacking Technology To Enable A Compact Energy Efficient Chip Multiprocessor

PicoServer : Using 3D Stacking Technology To Enable A Compact Energy Efficient Chip Multiprocessor PicoServer : Using 3D Stacking Technology To Enable A Compact Energy Efficient Chip Multiprocessor Taeho Kgil, Shaun D Souza, Ali Saidi, Nathan Binkert, Ronald Dreslinski, Steve Reinhardt, Krisztian Flautner,

More information

Uniprocessor Computer Architecture Example: Cray T3E

Uniprocessor Computer Architecture Example: Cray T3E Chapter 2: Computer-System Structures MP Example: Intel Pentium Pro Quad Lab 1 is available online Last lecture: why study operating systems? Purpose of this lecture: general knowledge of the structure

More information

EXASCALE COMPUTING: WHERE OPTICS MEETS ELECTRONICS

EXASCALE COMPUTING: WHERE OPTICS MEETS ELECTRONICS EXASCALE COMPUTING: WHERE OPTICS MEETS ELECTRONICS Overview of OFC Workshop: Organizers: Norm Jouppi HP Labs, Moray McLaren HP Labs, Madeleine Glick Intel Labs March 7, 2011 1 AGENDA Introduction. Moray

More information

Stacked Silicon Interconnect Technology (SSIT)

Stacked Silicon Interconnect Technology (SSIT) Stacked Silicon Interconnect Technology (SSIT) Suresh Ramalingam Xilinx Inc. MEPTEC, January 12, 2011 Agenda Background and Motivation Stacked Silicon Interconnect Technology Summary Background and Motivation

More information

The Memory Hierarchy 1

The Memory Hierarchy 1 The Memory Hierarchy 1 What is a cache? 2 What problem do caches solve? 3 Memory CPU Abstraction: Big array of bytes Memory memory 4 Performance vs 1980 Processor vs Memory Performance Memory is very slow

More information

Silicon Based Packaging for 400/800/1600 Gb/s Optical Interconnects

Silicon Based Packaging for 400/800/1600 Gb/s Optical Interconnects Silicon Based Packaging for 400/800/1600 Gb/s Optical Interconnects The Low Cost Solution for Parallel Optical Interconnects Into the Terabit per Second Age Executive Summary White Paper PhotonX Networks

More information

Evaluating Bufferless Flow Control for On-Chip Networks

Evaluating Bufferless Flow Control for On-Chip Networks Evaluating Bufferless Flow Control for On-Chip Networks George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis Stanford University In a nutshell Many researchers report high buffer

More information

Interconnection Networks

Interconnection Networks Lecture 15: Interconnection Networks Parallel Computer Architecture and Programming CMU 15-418/15-618, Spring 2016 Credit: some slides created by Michael Papamichael, others based on slides from Onur Mutlu

More information

NoC Round Table / ESA Sep Asynchronous Three Dimensional Networks on. on Chip. Abbas Sheibanyrad

NoC Round Table / ESA Sep Asynchronous Three Dimensional Networks on. on Chip. Abbas Sheibanyrad NoC Round Table / ESA Sep. 2009 Asynchronous Three Dimensional Networks on on Chip Frédéric ric PétrotP Outline Three Dimensional Integration Clock Distribution and GALS Paradigm Contribution of the Third

More information

Designing Multi-socket Systems Using Silicon Photonics

Designing Multi-socket Systems Using Silicon Photonics Designing Multi-socket Systems Using Silicon Photonics Scott Beamer Krste Asanovic Chris Batten Ajay Joshi Vladimir Stojanovic Electrical Engineering and Computer Sciences University of California at Berkeley

More information

Toward a unified architecture for LAN/WAN/WLAN/SAN switches and routers

Toward a unified architecture for LAN/WAN/WLAN/SAN switches and routers Toward a unified architecture for LAN/WAN/WLAN/SAN switches and routers Silvano Gai 1 The sellable HPSR Seamless LAN/WLAN/SAN/WAN Network as a platform System-wide network intelligence as platform for

More information

REPORT DOCUMENTATION PAGE

REPORT DOCUMENTATION PAGE REPORT DOCUMENTATION PAGE Form Approved OMB NO. 0704-0188 Public Reporting burden for Ihis collection of information is estimated to average 1 hour per response, including the time for reviewing instructions,

More information