CMOS Photonic Processor-Memory Networks

Transcription

1 CMOS Photonic Processor-Memory Networks Vladimir Stojanović Integrated Systems Group Massachusetts Institute of Technology

2 Acknowledgments Krste Asanović, Rajeev Ram, Franz Kaertner, Judy Hoyt, Henry Smith, Erich Ippen Miloš Popović, Christopher Batten, Ajay Joshi, Hanqing Li Jason Orcutt, Anatoly Khilo, Ben Moss, Jie Sun, Jonathan Leu, Michael Georgas, Chen Sun, Cheryl Sorace, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Eugen Zgraggen Dr. Jag Shah - DARPA MTO Texas Instruments Dennis Buss and Tom Bonifield IBM and Trusted Foundry Intel Corporation 2

3 Manycore Socket Roadmap 64-tile system ( cores) - 4-way SIMD GHz TFlops on one chip - Need 5-10 TB/s of off-chip I/O - Even larger bisection bandwidth 2 cm Intel 48 core -Xeon 2 cm 3

4 Bandwidth, pin count and power scaling Package pin count 8 5GHz 2,4 cores 256 cores Need 16k pins in 2017 for HPC 2 TFlop/s signal 10 Gb/s/link 1 Byte/Flop 4

5 DIMM DIMM DIMM System Bottlenecks Socket Bottlenecks Power Number of I/O pins Board Bottlenecks CPU and Memory Power Routing Density Manycore system CPU Cache/ MC CPU Cache/ MC cores Interconnect Network CPU Cache/ MC Bottlenecks due to energy and bandwidth density limitations Interconnect Network Need to jointly optimize on-chip and off-chip interconnect network 5

6 DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM Electrical Baseline in 2016 Node Board 10 TFlop/s 512 GB 80 Tb/s mem BW CPU Power 1kW -> 100W Energy-efficiency 100 pj/flop -> 10pJ/Flop 200 W Cross-chip Processor + Router P DIMM DIMM DIMM DIMM R Request P P P P P P P P P P P P CPU 64 x 8 x 32 = 16k High-speed signal pins DIMM DIMM DIMM DIMM W I/O P P P P 1kW Compute Memory Power 1kW 200 W Cross-chip 400 W I/O 400 W Activate P Processor Router Memory Controller Response 512 x 1GB chips 8 chips per DIMM 1DIMM per memory channel Need at least 16 banks/chip to sustain BW 6 64 memory channels (controllers) 1.28 Tb/s per controller 160 Gb/s per chip (16 x 10 5pJ/b

7 Monolithic CMOS-Photonics in Computer Systems Supercomputers Si-photonics in advanced CMOS and process NO costly process changes Embedded apps Use photonics to solve both the socket and the board problems 7

8 Unified on-chip/off-chip photonic link Dense WDM improves bandwidth density Monolithic integration reduces energy cost No process changes - advanced foundries Bulk CMOS Thin BOX SOI Results from 32nm/45nm chips coming soon 8

9 Silicon photonics area and energy advantage Metric Energy (pj/b) Bandwidth density (Gb/s/μ) Global on-chip photonic link Global on-chip optimally repeated electrical link Off-chip photonic link (50 μ coupler pitch) Off-chip electrical SERDES (100 μ pitch) On-chip/off-chip seamless photonic link

10 Baseline electrical system architecture C = Core, DM = Module Mesh Router Router and Access Point Both cross-chip and I/O costly 10

11 Aggregation with Optical LMGS* network * Local Meshes to Global Switches Ci = Core in Group i, DM = Module, S = Crossbar switch Shorten cross-chip electrical Photonic both part cross-chip and off-chip 11

12 Photonic LMGS - U-shape 64-tile system w/ 16 groups, 16 Modules, 320 Gbps bi-di tile- module BW [Joshi et al PICA 2009] 12

13 Photonic LMGS - U-shape 64-tile system w/ 16 groups, 16 Modules, 320 Gbps bi-di tile- module BW 13

14 Photonic LMGS - U-shape 64-tile system w/ 16 groups, 16 Modules, 320 Gbps bi-di tile- module BW 14

15 Photonic LMGS - U-shape 64-tile system w/ 16 groups, 16 Modules, 320 Gbps bi-di tile- module BW 15

16 Photonic LMGS - U-shape 64 tiles 64 waveguides (for tile throughput = 128 b/cyc) 256 modulators per group 256 ring filters per group Total rings > 16K 0.32W (thermal tuning) 16

17 Through loss (db/ring) Photonic device requirements in LMGS - U-shape Waveguide loss (db/cm) Optical Laser Power Die Area Overhead Waveguide loss and Through loss limits for 2 W optical laser power 17

18 Photonic LMGS ring matrix vs u-shape LMGS ring matrix LMGS u-shape 0.64 W power for thermal tuning circuits (1 μw/ring/k) 2 W optical laser power Waveguide loss < 0.2 db/cm Through loss < db/ring 0.32 W power for thermal tuning circuits (1 μw/ring/k) 2 W optical laser power Waveguide loss < 1.5 db/cm Through loss < 0.02 db/ring [Batten et al Micro 2009] [Joshi et al PICA 2009] 18

19 Power-bandwidth tradeoff 2-3x better 8-10x better 1 group, OPF = 1 4 group, OPF = 1 16 group, OPF = 1 1 group, OPF = 4 4 group, OPF = 2 16 group, OPF = 1 Electrical with grouping Electrical with grouping and over-provisioning 19 Optical with grouping and over-provisioning

20 Power-bandwidth tradeoff 2-3x better 8-10x better Cross-chip I/O Compute 6 W 10 W 100W 1 group, OPF = 1 4 group, OPF = 1 16 group, OPF = 1 1 group, OPF = 4 4 group, OPF = 2 16 group, OPF = 1 Electrical with grouping Electrical with grouping and over-provisioning 20 Optical with grouping and over-provisioning

21 System Organization Defragmentation [Beamer et al ICS 2009] Processor in cube Network Example 256 core node with 64 core dies 21

22 System Organization Defragmentation (processor in cube) 64 core die supporting 256 core node 22

23 Mem Scheduler Laser in Photonic Network Organization Super DIMM CPU cube 1 Important Concepts MC 1 cube 4 - Power/message switching (only to active chip in cube/super DIMM) MC K Dwr Drd cmd Dwr Drd ( cube 1, die 8) - Vertical die-to-die coupling (minimizes cabling - 8 dies per cube) die-die switch cmd Dwr Drd ( cube 1, die 1) Super DIMM K -Command distributed electrically (broadcast) - Data photonic (single writer multiple readers) cube 4 Modulator bank MC 16 Receiver/PD bank Tunable filterbank Through silicon via Through silicon via hole 23 [Beamer et al - UCB/EECS ]

24 network: Summary of Improvements 1kW 650 W System Memory Power Cross-chip Activate I/O 275 W 185 W 110 W Electrical Baseline Electrical Cache-line per chip Photonic I/O Cache-line per chip Photonic I/O and Cross-chip, Cache-line per chip Reduce Activate Energy Fetch cache-line from one chip in a DIMM Reduce I/O Energy with photonic links Reduce Cross-chip Energy with photonic links Reduce Fixed Energy with dynamic tuning/heater management 24

25 Conclusions Biggest gains if photonics both on-chip and off-chip Core-to-MC network MC-to- bank network Logical and physical topology significantly affects photonic device requirements Ring through losses, waveguide loss, crossings For system-wide gains, need optics in/to Need aggressive laser-power and circuit clock/static power management on unused links 25