DEMO MANUAL DC2579A LTC4279 Single Port UltraPWR PSE Controller. Description

Transcription

1 Description Demonstration Circuit 579A features the LTC 79, an autonomous single port power sourcing equipment (PSE) controller, configured in its UltraPWR mode. UltraPWR mode aggressively turns on and powers custom high power PDs requiring high inrush and/or operational currents. The DC579A requires a single power supply and provides power on all four Ethernet pairs to valid detected PDs. Jumper selections are provided on the DC579A for DEMO MANUAL DC579A LTC79 Single Port UltraPWR PSE Controller setting the LTC79 LEGACY pin, DUALPD pin and MID pin. A pushbutton switch resets the LTC79. LEDs indicate main supply power and output power are up. Data-In RJ5 connects to a PHY data source and Data-and-Power- Out RJ5 connects to a custom high power PD. Design files for this circuit board are available at L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. RJ5 DATA AND POWER OUT TO PD + RJ5 DATA IN FROM PHY DC579 F0 Figure. DC579A Connections dc579af

2 DEMO MANUAL DC579A Quick Start Procedure Demonstration circuit 579A is easy to setup for evaluating the performance of the LTC79. Refer to Figure for proper measurement equipment setup, Table for supply settings, and follow the procedure below.. Select HI at LEGACY jumper JP to enable LEGACY mode or select LO to disable LEGACY mode.. Select HI at DUALPD jumper JP to enable DUALPD mode or select LO to disable DUALPD mode.. Select HI at MID jumper JP to enable midspan mode or select LO to disable midspan mode.. Connect a power supply with the positive to AGND (J) and negative to (J). 5. Ramp up the supply to within the range specified in Table for the configured mode. LED will turn on when the board is powered. Table. Power Supply Range SELV Required Yes No MAIN PS Range 55V 60V 55V 65V 6. Connect test measurement probes across DATA+ to DATA, and DATA+ to DATA for port output measurements. 7. Connect a custom high power PD with a Cat5E Ethernet cable to RJ5 connector J. PORT PWR LED will turn on if the port power is on. 8. Connect a 0BASE-T, 00BASE-T or 000BASE-T PHY data source with an Ethernet cable to J for data testing (optional). Note: Any change in the jumper selections while power is on will require a power cycle or pushbutton reset for the change to take effect. Operation Power Control The primary function of the LTC79 is to control the delivery of power to the PSE port. It does this by controlling the gate drive voltage of an external power MOSFET (Q) while monitoring the current via an external sense resistor (RS) and the output voltage at the OUT pin. This circuitry serves to couple the raw input supply to the port in a controlled manner that satisfies the PD s power needs while minimizing both power dissipation in the MOSFET and disturbances on the backplane. UltraPWR Mode The LTC79 is configured for UltraPWR mode by a.0k resistor (RPM) from the PWRMODE pin to. Unlike LTPoE++ and the IEEE 80.at standard, UltraPWR is not a system defined standard. A PSE in UltraPWR mode issues up to three class events and powers valid detected PDs with maximum deliverable power, as determined by the PSE output voltage, V PSE. Warning: UltraPWR mode is not IEEE compliant. Certain existing very high power PDs proprietary to the PD manufactures benefit from the UltraPWR mode of the LT79. The LTC79 in UltraPWR mode simply provides very high power to these proprietary PDs. Figure (UltraPWR Power vs V PSE ) in the LTC79 data sheet shows PSE source power (at the PSE RJ5 jack) and PD delivered power (at the PD RJ5 jack) vs V PSE. The gray shaded area above 60V shows voltages exceeding SELV maximum; systems exceeding SELV maximum voltage may incur additional regulatory hurdles. Data In/Data And Power Out The DC579A can be set up in a midspan PSE configuration for data and power evaluation. A PD is connected with a Cat5e cable to DATA AND POWER OUT RJ5 connector (J). Power is injected on to the Ethernet lines through the center taps of the 000BASE-T Ethernet transformer (T). A 0BASE-T, 00BASE-T or 000BASE-T PHY data source is connected with an Ethernet cable to DATA IN RJ5 connector J for optional data testing. Data is passed from J to J along with the injected power. dc579af

3 DEMO MANUAL DC579A Operation LED Indicators The LED across the main power supply input indicates the DC579A is powered. The PORT PWR LED is connected from the AGND_P node to the LTC79 LED open-drain output pin. The LED pin pulls low and turns on LED when the port is powered. Each LED has a current limiting resistor in series. Test Points Test turrets on the DC579A are provided to connect test measurement equipment across the main supply (AGND and ), and -pair configured output (DATA+ and DATA, DATA+ and DATA ). If using an oscilloscope, connect the scope probe ground leads to a common point or use isolated differential probes for multiple channels with different ground references. RESET The DC579A pushbutton switch (SW) momentarily connects the LTC79 RESET pin to when pushed and released. When the RESET pin is logic low, the LTC79 is held inactive with the port off. When the RESET pin is released logic high, the LTC79 restarts normal operation. An external RC network at the LTC79 RESET pin on the DC579A provides a power turn-on delay. MID The DC579A MID jumper (JP) ties the LTC79 MID pin high to the AGND_P node or low to. When MID is high, the LTC79 acts as a midspan device with the Midspan Mode Detection Backoff timer enabled. When MID is low, the LTC79 acts as an endpoint device with the Midspan Mode Detection Backoff timer disabled. The LTC79 MID pin is internally pulled down to if the shunt at JP is removed. DUALPD The DC579A DUALPD jumper (JP) ties the LTC79 DUALPD pin high to the AGND_P node or low to. When DUALPD is high, the LTC79 detects, classifies and powers dual-signature PDs. Valid dual-signature PDs are present when two Type PD signatures are detected and classified in parallel. When the LTC79 DUALPD pin is low, dual-signature PD support is disabled. The LTC79 DUALPD pin is internally pulled down to if the shunt at JP is removed. Warning: Dual-signature detect, class and power on is not IEEE compliant. LEGACY The DC579A LEGACY jumper (JP) ties the LTC79 LEGACY pin high to the AGND_P node for enabling LEG- ACY mode, or low to for disabling LEGACY mode. See the LTC79 data sheet for further details on LEGACY mode. The LTC79 LEGACY pin is internally pulled down to if the shunt at JP is removed. Warning: Legacy detect is, by definition, not IEEE compliant. Logic Pin Protection The DC579A has a 00Ω resistor (R6, R7 and R8) in series from each of the LTC79 logic pins (MID, DUALPD and LEGACY) and to their respective jumpers (JP, JP and JP). These resistors provide current limit protection against high voltage transients when moving the shunt position at the jumper. In the end application, if the logic pin is hard tied high to the LTC79 AGND pin or hard tied low to, this resistor is not required. Surge Protection Ethernet ports can be subject to significant cable surge events. To keep PoE voltages below a safe level and protect the application against damage, protection components are required at the main supply, at the LTC79 supply pins, and at the output port. On the DC579A, a bulk transient voltage suppression diode (D) and a bulk capacitance (C5) are across the main PoE supply and absorb a majority of the surge energy coming in to the LTC79. In the end application, these should be sized to accommodate system surge energy requirements. The LTC79 requires a 0Ω, 0805 resistor (R0) in series from supply AGND to the LTC79 AGND pin for added surge protection. Across the LTC79 AGND pin and pin are a local SMAJ58A, 58V TVS (D) and a μf, 00V bypass capacitor (C) component, both placed close to the LTC79 pins. An SB standard rectifier diode (00V, A) provides reverse polarity protection at the port output as shown at D on the DC579A. dc579af

4 DEMO MANUAL DC579A Operation MOSFET and Gate RC Network The DC79A external Hot Swap MOSFET and gate RC network have been selected to meet loop stability and harsh current foldback conditions. Using different component values is not recommended. KELVIN Sense Proper connection of the port current sense lines is important for current threshold accuracy and IEEE compliance. On the DC579A, the LTC79 VSSK pin is connected to a Kelvin sense trace that leads to the sense resistor pad and is not connected directly to copper areas. Similarly, the LTC79 SENSE pin is connected to a Kelvin sense trace that leads to the sense resistor pad and is not connected in the power path between the sense resistor and the MOSFET. Figure highlights in red these two Kelvin traces from the LTC79 (U) to the sense resistor (RS). The LTC79 pins and the sense resistor pad connect to the copper areas. Figure. DC579 Kelvin Sense dc579af

5 DEMO MANUAL DC579A PCB Layout Top Silkscreen Layer Top Layer dc579af 5

6 DEMO MANUAL DC579A PCB Layout Layer AGND + CGND Plane Layer + CGND Plane 6 dc579af

7 DEMO MANUAL DC579A PCB Layout Layer Bottom Layer Bottom Silkscreen dc579af 7

8 DEMO MANUAL DC579A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER Required Circuit Components CGD CAP., 0.07µF, X7R, 00V, 0%, 0805 TDK, C0X7RA7M5AA CT, CT, CT, CT CAP, 0.0µF, X7R, 00V, 0%, 0805 MURATA, GRMBR7D0KW0L C, C CAP, 000pF, X7R, kv, 0%, 808 MURATA, GRQR7D0KW0L C CAP, 00pF, X7R, kv, 0%, 8 MURATA, GRQR7DKW0L 5 C CAP, µf, X7R, 00V, 0%, 06 MURATA, GRMCR7A05KA0L 6 C5 CAP., ELECT., 70µF 00V, CAP-PANA-NHG-6X5 PANASONIC, ECAAHG7 7 C6, C7 CAP., 0.µF, X7R, 00V, 0%, 0805 MURATA, GRMAR7AKAC5L 8 D DIODE, TVS, 00W, 70V, SMA-DIODE DIODES INC., SMAJ70A--F 9 D DIODE, TVS, 600W, 70V, SMB-DIODE DIODES INC., SMBJ70A--F 0 D DIODE, RECTIFIER, LOW LEAKAGE, SMA-DIODE FAIRCHILD SEMI., SB 6 E-E6 TEST POINT, TURRET, 0.09", MTG. HOLE MILL-MAX, JP, JP, JP CONN., HEADER, MALE, X, mm, THT WURTH ELEKTRONIK 6000 J, J CONN, RJ5, RJ5-WE WURTH ELEKTRONIK, J, J CONN, JACK, BANANA KEYSTONE, LED LED, YELLOW, LED-ROHM-SML-0 ROHM, SML-0Y8TT86 6 LED LED, GREEN, LED-ROHM-SML-0 ROHM, SML-0P8TT86 7 Q MOSFET, N-CH, 00V.8mΩ, DPAK NXP, PSMNR8-00BSEJ 8 RGD RES., 0Ω, %, /0W, 060 VISHAY, CRCW0600RFKEA 9 RG RES., 00Ω, %, /0W, 060 VISHAY, CRCW06000RFKEA 0 RPM RES.,.0kΩ, %, /0W, 060 VISHAY, CRCW060K0FKEA RS RES., SENSE, 0.Ω, %, W, 5 STACKPOLE, CSRN5FTR00 8 RX-RX, RT-RT RES., 75Ω, 5%, /0W, 060 VISHAY, CRCW06075R0JNEA R, R RES., 0Ω, /0W, 060 VISHAY, CRCW Z0EA R, R RES., kω, 5%, /W, 06 VISHAY, CRCW06K0JNEAHP 5 R5 RES., 00kΩ, 5%, /0W, 060 VISHAY, CRCW06000KJNEA 6 R6, R7, R8 RES., 00Ω, 5%, /0W, 060 VISHAY, CRCW06000RJNEA 7 R0 RES., 0Ω, 5%, /0W, 0805 VISHAY, CRCW08050R0JNEA 8 R-R RES., 0Ω, /W, 06 VISHAY, CRCW060000Z0EA 9 SW SWITCH, LIGHT TOUCH, SW-WE WURTH ELEKTRONIK, T XFMR, PoE PLUS ETHERNET MAGNETICS, WURTH ELEKTRONIK, 7900 TRANS-WE-7900 U IC, QFN0UFD-X5 LINEAR TECH., LTC79IUFD#PBF SHUNTS FOR JP-JP SHUNT, mm WURTH ELEKTRONIK, PINS AND MH-MH STAND-OFF, NYLON, 0.5" WURTH ELEKTRONIK, FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT #579A 5 STENCILS FOR BOTH SIDES STENCIL DC579A- 8 dc579af

9 5 5 DEMO MANUAL DC579A Schematic Diagram NOTE: UNLESS OTHERWISE SPECIFIED. ALL RESISTORS ARE IN OHMS, 060. ALL CAPACITORS ARE IN MICROFARADS, 060. REVISION HISTORY ECO REV DESCRIPTION APPROVED DATE PRODUCTION DILIAN R J J 0 DATA IN DATA AND POWER OUT D RX 75 D RT 75 CT 0.0uF. INSTALL SHUNTS AS SHOWN V R 0 0 RJ5, WE C 000pF kv 808 RX 75 RX 75 RX 75 0 T RT 75 RT 75 RT 75 CT 0.0uF V CT 0.0uF V CT 0.0uF V C 000pF kv 808 C 00pF kv 8 0 RJ5, WE R 0 (+) AGND J R0 E 0 C C AGND 0805 AGND_P R LED 0 06 E YELLOW VPORT- D PORT PWR DATA- C SMAJ70A uf LED 00V GREEN 06 MAIN PS R R U 0 06 E5 k R DATA+ INPUTS LTC79 DATA+ /W k 06 /W 06 RESET_N 8 LED ( 56V TO 65V ) RESET LED 0 MID 9 MID DNC 0 R DATA- DUALPD 6 DNC E6 D DUALPD DNC DATA- + C5 D 70uF SMBJ70A LEGACY 5 DNC LEGACY DNC SB 00V PWRMODE DNC PWRMODE DNC DNC X P R 0 06 VPORT+ E DATA+ B B 00V X7R 0805 SENSE GATE (-) AGND_P MID R6 DUALPD R7 LEGACY R8 RESET_N HI 00 MID HI 00 DUALPD HI 00 LEGACY 60 McCarthy Blvd. CUSTOMER NOTICE A APPROVALS Milpitas, CA 9505 A LO LO LO LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A Phone: (08) C7 JP JP JP CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; TECHNOLOGY Fax: (08)-0507 HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO RESET 0.uF HDX-079 HDX-079 HDX-079 PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL KIM T. LTC Confidential-For Customer Use Only 00V SW X7R APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. DILIAN R. TITLE: SCHEMATIC 0805 CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NONE SIZE N/A DATE: SINGLE PORT UltraPWR PSE CONTROLLER LTC79IUFD IC NO. REV. DEMO CIRCUIT 579A Monday, July 0, 07 SHEET OF RPM.0k RG 00 CGD 0.07uF 00V 0805 Q PSMNR8-00BSE VSSK SENSE GATE OUT AGND 9 C6 0.uF RS 0. %, W J R5 00k E RGD 0 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. dc579af 9

10 DEMO MANUAL DC579A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 0 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 60 McCarthy Blvd. Milpitas, CA 9505 Copyright 00, Linear Technology Corporation 0 dc579af LT 07 PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 07