MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1

Transcription

1 MC68HC908QY MC68HC908QT MC68HC908QY MC68HC908QT MC68HC908QY1 MC68HC908QT1 Data Sheet M68HC08 Microcontrollers MC68HC908QY/D Rev. 6 0/010 freescale.com

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3 MC68HC908QY MC68HC908QT MC68HC908QY MC68HC908QT MC68HC908QY1 MC68HC908QT1 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash technology licensed from SST. Freescale Semiconductor, Inc., All rights reserved. Freescale Semiconductor

4 Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History (Sheet 1 of ) Date September, 00 December, 00 January, 00 Revision Level Description Page Number(s) N/A Initial release N/A Features Added 8-pin dual flat no lead (DFN) packages to features list. 19 Figure 1-. MCU Pin Assignments Figure updated to include DFN packages. 1 Figure -1. Memory Map Clarified illegal address and unimplemented memory. 7 Figure -. Control, Status, and Data Registers Corrected bit definitions for Port A Data Register (PTA) and Data Direction Register A (DDRA). 7 Table 1-. Interrupt Sources Corrected vector addresses for keyboard interrupt and ADC conversion complete interrupt. 118 Chapter 1 System Integration Module (SIM) Removed reference to break status register as it is duplicated in break module Internal Oscillator and Internal Oscillator Trimming Clarified oscillator trim option ordering information and what to expect with untrimmed 9 device. Figure 11-. Oscillator Trim Register (OSCTRIM) Bit 1 designation corrected. 98 Figure 1-1. Monitor Mode Circuit (Internal Clock, No High Voltage) Diagram updated for clarity. 10 Figure 1-1. I/O Port Register Summary Corrected bit definitions for PTA7, DDRA7, and DDRA6. 99 Figure 1-. Port A Data Register (PTA) Corrected bit definition for PTA Figure 1-. Data Direction Register A (DDRA) Corrected bit definitions for DDRA7 and DDRA Figure 1-6. Port B Data Register (PTB) Corrected bit definition for PTB1 10 Chapter 9 Keyboard Interrupt Module (KBI) Section reworked after deletion of auto wakeup for clarity. 8 Chapter Auto Wakeup Module (AWU) New section added for clarity. 9 Figure LVI Module Block Diagram Corrected LVI stop representation. 87 Chapter 16 Electrical Specifications Extensive changes made to electrical specifications Pin Dual Flat No Lead (DFN) Package (Case #1) Added case outline drawing for DFN package. 177 Chapter 17 Ordering Information and Mechanical Specifications Added ordering information for DFN package Features Corrected third bulleted item. 9 Freescale Semiconductor

5 Revision History (Sheet of ) Date August, 00 October, 00 January, 00 Revision Level Description Reformatted to meet latest M68HC08 documentation standards Page Number(s) Figure 1-1. Block Diagram Diagram redrawn to include keyboard interrupt module and TCLK pin designator. 0 Figure 1-. MCU Pin Assignments Added TCLK pin designator. 1 Table 1-. Pin Functions Added TCLK pin description. Table 1-. Function Priority in Shared Pins Revised table for clarity and to add TCLK. Figure -1. Memory Map Corrected names for the IRQ status and control register (INTSCR) bits ADC Input Clock Register Clarified bit description for the ADC clock prescaler bits. 7. Functional Description Updated periodic wakeup request values. 1 Figure 6-1. COP Block Diagram Reworked for clarity 9 Chapter 8 External Interrupt (IRQ) Corrected bit names for MODE, IRQF, ACK, and IMASK Chapter 1 Timer Interface Module (TIM) Added TCLK function Monitor Module (MON) Updated with additional data. 17 Chapter 16 Electrical Specifications Updated with additional data Figure -. Control, Status, and Data Registers Deleted unimplemented areas from $FFB0 $FFBD and $FFC $FFCF as they are actually available. 7 Also corrected $FFBF designation from unimplemented to reserved. Figure 6-1. COP Block Diagram Reworked for clarity STOP Instruction Added subsection Active Resets from Internal Sources Reworked notes for clarity. 111 Table 1-. Reset Recovery Timing Replaced previous table with new information. 11 Chapter 1 Timer Interface Module (TIM) Updated with additional data. 11 Figure 1-. Break I/O Register Summary Corrected bit designators for the BRKAR register 1 1. Monitor Module (MON) Clarified seventh bullet. 17 Table MC Order Numbers Corrected temperature and package designators. 17 Figure -. Control, Status, and Data Registers Corrected reset state for the FLASH Block Protect Register at address location $FFBE and the Internal Oscillator Trim Value at $FFC0. Figure -. FLASH Block Protect Register (FLBPR) Restated reset state for clarity. 8 N/A Freescale Semiconductor

6 Revision History Revision History (Sheet of ) Date November, 00 July, 00 March, 010 Revision Level Description Reformatted to meet current documentation standards Throughout 6..1 BUSCLKX Clarified description of BUSCLKX 8 Chapter 7 Central Processor Unit (CPU) In 7.7 Instruction Set Summary: Reworked definitions for STOP instruction Added WAIT instruction Page Number(s) SIM Reset Status Register Clarified SRSR flag setting TIM Status and Control Register Added information to TSTOP note V Oscillator Characteristics Added values for deviation from trimmed inernal oscillator V Oscillator Characteristics Added values for deviation from trimmed inernal oscillator 18 Figure -. Configuration Register 1 (CONFIG1) Clarified bit definitions for COPRS. Chapter 8 External Interrupt (IRQ) Reworked for clarification RC Oscillator Improved RC oscillator wording Introduction Added note pertaining to non-bonded port pins Package Dimensions Updated package information. 16 6, 7, 1, 6.0 Clarify internal oscillator trim register information.,, 8, 91, Freescale Semiconductor

7 List of Chapters Chapter 1 General Description Chapter Memory Chapter Analog-to-Digital Converter (ADC) Chapter Auto Wakeup Module (AWU) Chapter Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Voltage Inhibit (LVI) Chapter 11 Oscillator Module (OSC) Chapter 1 Input/Output Ports (PORTS) Chapter 1 System Integration Module (SIM) Chapter 1 Timer Interface Module (TIM) Chapter 1 Development Support Chapter 16 Electrical Specifications Chapter 17 Ordering Information and Mechanical Specifications Freescale Semiconductor 7

8 List of Chapters 8 Freescale Semiconductor

9 Table of Contents Chapter 1 General Description 1.1 Introduction Features MCU Block Diagram Pin Assignments Pin Functions Pin Function Priority Chapter Memory.1 Introduction Unimplemented Memory Locations Reserved Memory Locations Input/Output (I/O) Section Random-Access Memory (RAM) FLASH Memory (FLASH) FLASH Control Register FLASH Page Erase Operation FLASH Mass Erase Operation FLASH Program Operation FLASH Protection FLASH Block Protect Register Wait Mode Stop Mode Chapter Analog-to-Digital Converter (ADC).1 Introduction Features Functional Description ADC Port I/O Pins Voltage Conversion Conversion Time Continuous Conversion Accuracy and Precision Interrupts Low-Power Modes Wait Mode Stop Mode Freescale Semiconductor 9

10 Table of Contents.6 Input/Output Signals Input/Output Registers ADC Status and Control Register ADC Data Register ADC Input Clock Register Chapter Auto Wakeup Module (AWU).1 Introduction Features Functional Description Wait Mode Stop Mode Input/Output Registers Port A I/O Register Keyboard Status and Control Register Keyboard Interrupt Enable Register Chapter Configuration Register (CONFIG).1 Introduction Functional Description Chapter 6 Computer Operating Properly (COP) 6.1 Introduction Functional Description I/O Signals BUSCLKX STOP Instruction COPCTL Write Power-On Reset Internal Reset COPD (COP Disable) COPRS (COP Rate Select) COP Control Register Interrupts Monitor Mode Low-Power Modes Wait Mode Stop Mode COP Module During Break Mode Freescale Semiconductor

11 Chapter 7 Central Processor Unit (CPU) 7.1 Introduction Features CPU Registers Accumulator Index Register Stack Pointer Program Counter Condition Code Register Arithmetic/Logic Unit (ALU) Low-Power Modes Wait Mode Stop Mode CPU During Break Interrupts Instruction Set Summary Opcode Map Chapter 8 External Interrupt (IRQ) 8.1 Introduction Features Functional Description MODE = MODE = Interrupts Low-Power Modes Wait Mode Stop Mode IRQ Module During Break Interrupts I/O Signals IRQ Input Pins (IRQ) Registers Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction Features Functional Description Keyboard Operation Keyboard Initialization Wait Mode Stop Mode Keyboard Module During Break Interrupts Freescale Semiconductor 11

12 Table of Contents 9.7 Input/Output Registers Keyboard Status and Control Register Keyboard Interrupt Enable Register Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction Features Functional Description Polled LVI Operation Forced Reset Operation Voltage Hysteresis Protection LVI Trip Selection LVI Status Register LVI Interrupts Low-Power Modes Wait Mode Stop Mode Chapter 11 Oscillator Module (OSC) 11.1 Introduction Features Functional Description Internal Oscillator Internal Oscillator Trimming Internal to External Clock Switching External Oscillator XTAL Oscillator RC Oscillator Oscillator Module Signals Crystal Amplifier Input Pin (OSC1) Crystal Amplifier Output Pin (OSC/PTA/BUSCLKX) Oscillator Enable Signal (SIMOSCEN) XTAL Oscillator Clock (XTALCLK) RC Oscillator Clock (RCCLK) Internal Oscillator Clock (INTCLK) Oscillator Out (BUSCLKX) Oscillator Out (BUSCLKX) Low Power Modes Wait Mode Stop Mode Oscillator During Break Mode CONFIG Options Input/Output (I/O) Registers Oscillator Status Register Oscillator Trim Register (OSCTRIM) Freescale Semiconductor

13 Chapter 1 Input/Output Ports (PORTS) 1.1 Introduction Port A Port A Data Register Data Direction Register A Port A Input Pullup Enable Register Port B Port B Data Register Data Direction Register B Port B Input Pullup Enable Register Chapter 1 System Integration Module (SIM) 1.1 Introduction RST and IRQ Pins Initialization SIM Bus Clock Control and Generation Bus Timing Clock Start-Up from POR Clocks in Stop Mode and Wait Mode Reset and System Initialization External Pin Reset Active Resets from Internal Sources Power-On Reset Computer Operating Properly (COP) Reset Illegal Opcode Reset Illegal Address Reset Low-Voltage Inhibit (LVI) Reset SIM Counter SIM Counter During Power-On Reset SIM Counter During Stop Mode Recovery SIM Counter and Reset States Exception Control Interrupts Hardware Interrupts SWI Instruction Interrupt Status Registers Interrupt Status Register Interrupt Status Register Interrupt Status Register Reset Break Interrupts Status Flag Protection in Break Mode Low-Power Modes Wait Mode Stop Mode Freescale Semiconductor 1

14 Table of Contents 1.8 SIM Registers SIM Reset Status Register Break Flag Control Register Chapter 1 Timer Interface Module (TIM) 1.1 Introduction Features Pin Name Conventions Functional Description TIM Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Buffered Output Compare Pulse Width Modulation (PWM) Unbuffered PWM Signal Generation Buffered PWM Signal Generation PWM Initialization Interrupts Wait Mode TIM During Break Interrupts Input/Output Signals TIM Clock Pin (PTA/TCLK) TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1) Input/Output Registers TIM Status and Control Register TIM Counter Registers TIM Counter Modulo Registers TIM Channel Status and Control Registers TIM Channel Registers Chapter 1 Development Support 1.1 Introduction Break Module (BRK) Functional Description Flag Protection During Break Interrupts TIM During Break Interrupts COP During Break Interrupts Break Module Registers Break Status and Control Register Break Address Registers Break Auxiliary Register Break Status Register Break Flag Control Register Low-Power Modes Freescale Semiconductor

15 1. Monitor Module (MON) Functional Description Normal Monitor Mode Forced Monitor Mode Monitor Vectors Data Format Break Signal Baud Rate Commands Security Chapter 16 Electrical Specifications 16.1 Introduction Absolute Maximum Ratings Functional Operating Range Thermal Characteristics V DC Electrical Characteristics Typical -V Output Drive Characteristics V Control Timing V Oscillator Characteristics V DC Electrical Characteristics Typical.0-V Output Drive Characteristics V Control Timing V Oscillator Characteristics Supply Current Characteristics Analog-to-Digital Converter Characteristics Timer Interface Module Characteristics Memory Characteristics Chapter 17 Ordering Information and Mechanical Specifications 17.1 Introduction MC Order Numbers Package Dimensions Freescale Semiconductor 1

16 Table of Contents 16 Freescale Semiconductor

17 Chapter 1 General Description 1.1 Introduction The MC68HC908QY is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) with a Von Neumann architecture. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. Device 0. Table 1-1. Summary of Device Variations FLASH Memory Size Analog-to-Digital Converter Pin Count MC68HC908QT1 16 bytes 8 pins MC68HC908QT 16 bytes ch, 8 bit 8 pins MC68HC908QT 096 bytes ch, 8 bit 8 pins MC68HC908QY1 16 bytes 16 pins MC68HC908QY 16 bytes ch, 8 bit 16 pins MC68HC908QY 096 bytes ch, 8 bit 16 pins 1. Features Features include: High-performance M68HC08 CPU core Fully upward-compatible object code with M68HC0 Family -V and -V operating voltages (V DD ) 8-MHz internal bus operation at V, -MHz at V Trimmable internal oscillator. MHz internal bus operation 8-bit trim capability allows 0.% accuracy (1) ± % untrimmed Auto wakeup from STOP capability Configuration (CONFIG) register for MCU configuration options, including: Low-voltage inhibit (LVI) trip point In-system FLASH programming FLASH security () 1. The oscillator frequency is guaranteed to ±% over temperature and voltage range after trimming.. No security feature is absolutely secure. However, Freescale s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor 17

18 General Description On-chip in-application programmable FLASH memory (with internal program/erase voltage generation) MC68HC908QY and MC68HC908QT 096 bytes MC68HC908QY, MC68HC908QY1, MC68HC908QT, and MC68HC908QT1 16 bytes 18 bytes of on-chip random-access memory (RAM) -channel, 16-bit timer interface module (TIM) -channel, 8-bit analog-to-digital converter (ADC) on MC68HC908QY, MC68HC908QY, MC68HC908QT, and MC68HC908QT or 1 bidirectional input/output (I/O) lines and one input only: Six shared with keyboard interrupt function and ADC Two shared with timer channels One shared with external interrupt (IRQ) Eight extra I/O lines on 16-pin package only High current sink/source capability on all port pins Selectable pullups on all ports, selectable on an individual bit basis Three-state ability on all port pins 6-bit keyboard interrupt with wakeup feature (KBI) Low-voltage inhibit (LVI) module features: Software selectable trip point in CONFIG register System protection features: Computer operating properly (COP) watchdog Low-voltage detection with reset Illegal opcode detection with reset Illegal address detection with reset External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose input pin Master asynchronous reset pin (RST) shared with general-purpose input/output (I/O) pin Power-on reset Internal pullups on IRQ and RST to reduce external components Memory mapped I/O registers Power saving stop and wait modes MC68HC908QY, MC68HC908QY, and MC68HC908QY1 are available in these packages: 16-pin plastic dual in-line package (PDIP) 16-pin small outline integrated circuit (SOIC) package 16-pin thin shrink small outline package (TSSOP) MC68HC908QT, MC68HC908QT, and MC68HC908QT1 are available in these packages: 8-pin PDIP 8-pin SOIC 8-pin dual flat no lead (DFN) package 18 Freescale Semiconductor

19 MCU Block Diagram Features of the CPU08 include the following: Enhanced HC0 programming model Extensive loop control functions 16 addressing modes (eight more than the HC0) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Efficient C language support 1. MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QY. 1. Pin Assignments The MC68HC908QT, MC68HC908QT, and MC68HC908QT1 are available in 8-pin packages and the MC68HC908QY, MC68HC908QY, and MC68HC908QY1 in 16-pin packages. Figure 1- shows the pin assignment for these packages. Freescale Semiconductor 19

20 General Description PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA/IRQ/KBI/TCLK PTA/RST/KBI PTA DDRA CLOCK GENERATOR (OSCILLATOR) PTA/OSC/AD/KBI PTA/OSC1/AD/KBI PTB0 PTB1 PTB PTB PTB PTB PTB6 PTB7 PTB DDRB M68HC08 CPU SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 8-BIT ADC 18 BYTES RAM MC68HC908QY AND MC68HC908QT 096 BYTES MC68HC908QY, MC68HC908QY1, MC68HC908QT, AND MC68HC908QT1: 16 BYTES USER FLASH KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE POWER SUPPLY V DD V SS MONITOR ROM RST, IRQ: Pins have internal (about 0K Ohms) pull up PTA[0:]: High current sink and source capability PTA[0:]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices MC68HC908QT1, MC68HC908QT, and MC68HC908QT (see note in 1.1 Introduction) ADC: Not available on the MC68HC908QY1 and MC68HC908QT1 Figure 1-1. Block Diagram 0 Freescale Semiconductor

21 Pin Assignments V DD 1 8 V SS V DD 1 8 V SS PTA/OSC1/KBI 7 PTA0/TCH0/KBI0 PTA/OSC1/AD/KBI 7 PTA0/AD0/TCH0/KBI0 PTA/OSC/KBI 6 PTA1/TCH1/KBI1 PTA/OSC/AD/KBI 6 PTA1/AD1/TCH1/KBI1 PTA/RST/KBI PTA/IRQ/KBI/TCLK PTA/RST/KBI PTA/IRQ/KBI/TCLK 8-PIN ASSIGNMENT MC68HC908QT1 PDIP/SOIC 8-PIN ASSIGNMENT MC68HC908QT AND MC68HC908QT PDIP/SOIC V DD 1 16 V SS V DD 1 16 V SS PTB7 1 PTB0 PTB7 1 PTB0 PTB6 1 PTB1 PTB6 1 PTB1 PTA/OSC1/KBI 1 PTA0/TCH0/KBI0 PTA/OSC1/AD/KBI 1 PTA0/AD0/TCH0/KBI0 PTA/OSC/KBI 1 PTA1/TCH1/KBI1 PTA/OSC/AD/KBI 1 PTA1/AD1/TCH1/KBI1 PTB 6 11 PTB PTB 6 11 PTB PTB 7 10 PTB PTB 7 10 PTB PTA/RST/KBI 8 9 PTA/IRQ/KBI/TCLK PTA/RST/KBI 8 9 PTA/IRQ/KBI/TCLK 16-PIN ASSIGNMENT MC68HC908QY1 PDIP/SOIC 16-PIN ASSIGNMENT MC68HC908QY AND MC68HC908QY PDIP/SOIC PTA0/TCH0/KBI0 PTB1 PTB0 V SS V DD PTB7 PTB6 PTA/OSC1/KBI PTA1/TCH1/KBI1 PTB PTB PTA/IRQ/KBI/TCLK PTA/RST/KBI PTB PTB PTA/OSC/KBI PTA0/AD0/TCH0/KBI0 PTB1 PTB0 V SS V DD PTB7 PTB6 PTA/OSC1/AD/KBI PTA1/AD1/TCH1/KBI1 PTB PTB PTA/IRQ/KBI/TCLK PTA/RST/KBI PTB PTB PTA/OSC/AD/KBI 16-PIN ASSIGNMENT MC68HC908QY1 TSSOP 16-PIN ASSIGNMENT MC68HC908QY AND MC68HC908QY TSSOP PTA0/TCH0/KBI0 1 8 PTA1/TCH1/KBI1 PTA0/AD0/TCH0/KBI0 1 8 PTA1/AD1/TCH1/KBI1 V SS 7 PTA/IRQ/KBI/TCLK V SS 7 PTA/IRQ/KBI/TCLK V DD 6 PTA/RST/KBI V DD 6 PTA/RST/KBI PTA/OSC1/KB1 PTA/OSC/KBI PTA//OSC1/AD/KB1 PTA/OSC/AD/KBI 8-PIN ASSIGNMENT MC68HC908QT1 DFN 8-PIN ASSIGNMENT MC68HC908QT AND MC68HC908QT DFN Figure 1-. MCU Pin Assignments Freescale Semiconductor 1

22 General Description 1. Pin Functions Table 1- provides a description of the pin functions. Table 1-. Pin Functions Pin Name Description Input/Output V DD Power supply Power V SS Power supply ground Power PTA0 PTA1 PTA PTA PTA PTA PTA0 General purpose I/O port AD0 A/D channel 0 input TCH0 Timer Channel 0 I/O KBI0 Keyboard interrupt input 0 PTA1 General purpose I/O port AD1 A/D channel 1 input TCH1 Timer Channel 1 I/O KBI1 Keyboard interrupt input 1 PTA General purpose input-only port IRQ External interrupt with programmable pullup and Schmitt trigger input KBI Keyboard interrupt input TCLK Timer clock input PTA General purpose I/O port RST Reset input, active low with internal pullup and Schmitt trigger KBI Keyboard interrupt input PTA General purpose I/O port OSC XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSCEN = 1 in PTAPUE register) AD A/D channel input KBI Keyboard interrupt input PTA General purpose I/O port OSC1 XTAL, RC, or external oscillator input AD A/D channel input KBI Keyboard interrupt input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input Input Input Input Input/Output Input Input Input/Output Output Output Input Input Input/Output Input Input Input PTB[0:7] (1) 8 general-purpose I/O ports Input/Output 1. The PTB pins are not available on the 8-pin packages (see note in 1.1 Introduction). Freescale Semiconductor

23 1.6 Pin Function Priority Table 1- is meant to resolve the priority if multiple functions are enabled on a single pin. NOTE Upon reset all pins come up as input ports regardless of the priority table. Table 1-. Function Priority in Shared Pins Pin Function Priority Pin Name PTA0 PTA1 PTA PTA PTA PTA Highest-to-Lowest Priority Sequence AD0 TCH0 KBI0 PTA0 AD1 TCH1 KBI1 PTA1 IRQ KBI TCLK PTA RST KBI PTA OSC AD KBI PTA OSC1 AD KBI PTA Freescale Semiconductor

24 General Description Freescale Semiconductor

25 Chapter Memory.1 Introduction The central processor unit (CPU08) can address 6 Kbytes of memory space. The memory map, shown in Figure -1, includes: 096 bytes of user FLASH for MC68HC908QT and MC68HC908QY 16 bytes of user FLASH for MC68HC908QT, MC68HC908QT1, MC68HC908QY, and MC68HC908QY1 18 bytes of random access memory (RAM) 8 bytes of user-defined vectors, located in FLASH 16 bytes of monitor read-only memory (ROM) 16 bytes of FLASH program and erase routines, located in ROM. Unimplemented Memory Locations Accessing an unimplemented location can have unpredictable effects on MCU operation. In Figure -1 and in register figures in this document, unimplemented locations are shaded.. Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In Figure -1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R. Freescale Semiconductor

26 Memory $0000 $00F $000 $007F $0080 $00FF $0100 $7FF $800 $DFF $E00 $EDFF $EE00 $FDFF $FE00 $FE01 $FE0 $FE0 $FE0 $FE0 $FE06 $FE07 $FE08 $FE09 I/O REGISTERS 6 BYTES RESERVED (1) 6 BYTES RAM 18 BYTES UNIMPLEMENTED (1) 998 BYTES AUXILIARY ROM 16 BYTES UNIMPLEMENTED (1) 91 BYTES FLASH MEMORY MC68HC908QT AND MC68HC908QY 096 BYTES BREAK STATUS REGISTER (BSR) RESET STATUS REGISTER (SRSR) BREAK AUXILIARY REGISTER (BRKAR) BREAK FLAG CONTROL REGISTER (BFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER (INT) INTERRUPT STATUS REGISTER (INT) RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR) FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS HIGH REGISTER (BRKH) $FE0A BREAK ADDRESS LOW REGISTER (BRKL) $FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0C LVISR $FE0D RESERVED FOR FLASH TEST BYTES $FE0F $FE10 MONITOR ROM 16 BYTES $FFAF $FFB0 FLASH 1 BYTES $FFBD $FFBE FLASH BLOCK PROTECT REGISTER (FLBPR) $FFBF RESERVED FLASH $FFC0 INTERNAL OSCILLATOR TRIM VALUE (VDD =.0 V) $FFC1 INTERNAL OSCILLATOR TRIM VALUE (VDD =.0 V) $FFC $FFCF $FFD0 $FFFF FLASH 1 BYTES USER VECTORS 8 BYTES Figure -1. Memory Map Note 1. Attempts to execute code from addresses in this range will generate an illegal address reset. UNIMPLEMENTED 171 BYTES FLASH MEMORY 16 BYTES MC68HC908QT1, MC68HC908QT, MC68HC908QY1, and MC68HC908QY Memory Map $E00 $F7FF $F800 $FDFF 6 Freescale Semiconductor

27 Input/Output (I/O) Section. Input/Output (I/O) Section Addresses $0000 $00F, shown in Figure -, contain most of the control, status, and data registers. Additional I/O registers have these addresses: $FE00 Break status register, BSR $FE01 Reset status register, SRSR $FE0 Break auxiliary register, BRKAR $FE0 Break flag control register, BFCR $FE0 Interrupt status register 1, INT1 $FE0 Interrupt status register, INT $FE06 Interrupt status register, INT $FE07 Reserved $FE08 FLASH control register, FLCR $FE09 Break address register high, BRKH $FE0A Break address register low, BRKL $FE0B Break status and control register, BRKSCR $FE0C LVI status register, LVISR $FE0D Reserved $FFBE FLASH block protect register, FLBPR $FFC0 Internal OSC trim value (factory programmed, VDD =.0 V) $FFC1 Internal OSC trim value (factory programmed, VDD =.0 V) $FFFF COP control register, COPCTL Addr. Register Name Bit Bit 0 Port A Data Register Read: AWUL PTA R PTA PTA PTA PTA1 PTA0 $0000 (PTA) Write: See page 98. Reset: Unaffected by reset Port B Data Register Read: PTB7 PTB6 PTB PTB PTB PTB PTB1 PTB0 $0001 (PTB) Write: See page 100. Reset: Unaffected by reset $000 Unimplemented $000 Unimplemented $000 $000 Data Direction Register A (DDRA) See page 98. Data Direction Register B (DDRB) See page 101. Read: 0 R R DDRA DDRA DDRA Write: DDRA1 DDRA0 Reset: Read: Write: DDRB7 DDRB6 DDRB DDRB DDRB DDRB DDRB1 DDRB0 Reset: = Unimplemented R = Reserved U = Unaffected Figure -. Control, Status, and Data Registers (Sheet 1 of ) Freescale Semiconductor 7

28 Memory Addr. Register Name Bit Bit 0 $0006 $000A Unimplemented Unimplemented $000B $000C $000D $0019 Port A Input Pullup Enable Register (PTAPUE) See page 99. Port B Input Pullup Enable Register (PTBPUE) See page 10. Unimplemented Read: 0 OSCEN Write: PTAPUE PTAPUE PTAPUE PTAPUE PTAPUE1 PTAPUE0 Reset: Read: Write: PTBPUE7 PTBPUE6 PTBPUE PTBPUE PTBPUE PTBPUE PTBPUE1 PTBPUE0 Reset: $001A $001B Keyboard Status and Control Register (KBSCR) See page 8. Keyboard Interrupt Enable Register (KBIER) See page 8. $001C Unimplemented Read: KEYF 0 IMASKK MODEK Write: ACKK Reset: Read: 0 AWUIE KBIE KBIE KBIE KBIE KBIE1 KBIE0 Write: Reset: $001D $001E $001F $000 $001 IRQ Status and Control Register (INTSCR) See page 77. Configuration Register (CONFIG) (1) See page. Configuration Register 1 (CONFIG1) (1) See page. TIM Status and Control Register (TSC) See page 17. TIM Counter Register High (TCNTH) See page 18. Read: IRQF 0 Write: ACK IMASK Reset: Read: Write: MODE IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN Reset: () 1. One-time writable register after each reset.. RSTEN reset to 0 by a power-on reset (POR) only. Read: Write: COPRS LVISTOP LVIRSTD LVIPWRD LVIOR SSREC STOP COPD Reset: () One-time writable register after each reset.. LVIOR reset to 0 by a power-on reset (POR) only. Read: TOF 0 0 TOIE TSTOP Write: 0 TRST PS PS1 PS0 Reset: Read: Bit 1 Bit 1 Bit 1 Bit 1 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: = Unimplemented R = Reserved U = Unaffected Figure -. Control, Status, and Data Registers (Sheet of ) 8 Freescale Semiconductor

29 Input/Output (I/O) Section Addr. Register Name Bit Bit 0 $00 $00 $00 $00 $006 $007 $008 $009 $00A $00B $00 TIM Counter Register Low (TCNTL) See page 18. TIM Counter Modulo Register High (TMODH) See page 19. TIM Counter Modulo Register Low (TMODL) See page 19. TIM Channel 0 Status and Control Register (TSC0) See page 10. TIM Channel 0 Register High (TCH0H) See page 1. TIM Channel 0 Register Low (TCH0L) See page 1. TIM Channel 1 Status and Control Register (TSC1) See page 10. TIM Channel 1 Register High (TCH1H) See page 1. TIM Channel 1 Register Low (TCH1L) See page 1. Unimplemented Read: Bit 7 Bit 6 Bit Bit Bit Bit Bit 1 Bit 0 Write: Reset: Read: Write: Bit 1 Bit 1 Bit 1 Bit 1 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Read: Write: Bit 7 Bit 6 Bit Bit Bit Bit Bit 1 Bit 0 Reset: Read: CH0F Write: 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Reset: Read: Write: Reset: Read: Write: Reset: Read: Bit 1 Bit 1 Bit 1 Bit 1 Bit 11 Bit 10 Bit 9 Bit 8 Indeterminate after reset Bit 7 Bit 6 Bit Bit Bit Bit Bit 1 Bit 0 CH1F Write: 0 CH1IE 0 Indeterminate after reset MS1A ELS1B ELS1A TOV1 CH1MAX Reset: Read: Write: Reset: Read: Write: Reset: Bit 1 Bit 1 Bit 1 Bit 1 Bit 11 Bit 10 Bit 9 Bit 8 Indeterminate after reset Bit 7 Bit 6 Bit Bit Bit Bit Bit 1 Bit 0 Indeterminate after reset $006 Oscillator Status Register (OSCSTAT) See page 96. Read: Write: $007 Unimplemented Read: R R R R R R ECGON Reset: ECGST $008 Oscillator Trim Register (OSCTRIM) See page 96. Read: Write: TRIM7 TRIM6 TRIM TRIM TRIM TRIM TRIM1 TRIM0 Reset: = Unimplemented R = Reserved U = Unaffected Figure -. Control, Status, and Data Registers (Sheet of ) Freescale Semiconductor 9

30 Memory Addr. Register Name Bit Bit 0 $009 $00B Unimplemented $00C ADC Status and Control Register (ADSCR) See page. $00D Unimplemented Read: COCO AIEN ADCO CH CH CH CH1 CH0 Write: R Reset: $00E $00F $FE00 ADC Data Register (ADR) See page 7. ADC Input Clock Register (ADICLK) See page 7. Break Status Register (BSR) See page 17. Read: Bit 7 Bit 6 Bit Bit Bit Bit Bit 1 Bit 0 Write: Reset: Indeterminate after reset Read: ADIV ADIV1 ADIV0 Write: Reset: Read: SBSW R R R R R R R Write: See note 1 Reset: 0 1. Writing a 0 clears SBSW. $FE01 $FE0 $FE0 $FE0 $FE0 $FE06 SIM Reset Status Register (SRSR) See page 117. Break Auxiliary Register (BRKAR) See page 17. Break Flag Control Register (BFCR) See page 18. Interrupt Status Register 1 (INT1) See page 77. Interrupt Status Register (INT) See page 77. Interrupt Status Register (INT) See page 77. Read: POR PIN COP ILOP ILAD MODRST LVI 0 Write: POR: Read: Write: Reset: Read: Write: Reset: 0 BCFE R R R R R R R Read: 0 IF IF IF 0 IF1 0 0 Write: R R R R R R R R Reset: Read: IF Write: R R R R R R R R Reset: BDCOP Read: IF1 Write: R R R R R R R R Reset: $FE07 Reserved R R R R R R R R = Unimplemented R = Reserved U = Unaffected Figure -. Control, Status, and Data Registers (Sheet of ) 0 Freescale Semiconductor

31 Input/Output (I/O) Section Addr. Register Name Bit Bit 0 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0F FLASH Control Register (FLCR) See page. Break Address High Register (BRKH) See page 16. Break Address low Register (BRKL) See page 16. Break Status and Control Register (BRKSCR) See page 16. LVI Status Register (LVISR) See page 87. Read: Write: HVEN MASS ERASE PGM Reset: Read: Write: Bit 1 Bit 1 Bit 1 Bit 1 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Read: Write: Bit 7 Bit 6 Bit Bit Bit Bit Bit 1 Bit 0 Reset: Read: Write: BRKE BRKA Reset: Read: LVIOUT R Write: Reset: Reserved for FLASH Test R R R R R R R R $FFBE FLASH Block Protect Register (FLBPR) See page 9. Read: Write: Reset: BPR7 BPR6 BPR BPR BPR BPR BPR1 BPR0 Unaffected by reset $FFBF Reserved R R R R R R R R $FFC0 $FFC1 Internal Oscillator Trim (Factory Programmed, VDD =.0 V) Internal Oscillator Trim (Factory Programmed, VDD =.0 V) Read: Write: Reset: Read: Write: Reset: TRIM7 TRIM6 TRIM TRIM TRIM TRIM TRIM1 TRIM0 Unaffected by reset TRIM7 TRIM6 TRIM TRIM TRIM TRIM TRIM1 TRIM0 Unaffected by reset $FFFF COP Control Register (COPCTL) See page 9. Read: Write: Reset: LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure -. Control, Status, and Data Registers (Sheet of ) Freescale Semiconductor 1

32 Memory. Table -1. Vector Addresses Vector Priority Vector Address Vector Lowest $FFDE ADC conversion complete vector (high) IF1 $FFDF ADC conversion complete vector (low) IF1 $FFE0 Keyboard vector (high) $FFE1 Keyboard vector (low) IF1 IF6 Not used IF $FFF TIM overflow vector (high) $FFF TIM overflow vector (low) IF $FFF TIM Channel 1 vector (high) $FFF TIM Channel 1 vector (low) IF $FFF6 TIM Channel 0 vector (high) $FFF7 TIM Channel 0 vector (low) IF Not used IF1 $FFFA IRQ vector (high) $FFFB IRQ vector (low) $FFFC SWI vector (high) $FFFD SWI vector (low) $FFFE Reset vector (high) Highest $FFFF Reset vector (low). Random-Access Memory (RAM) Addresses $0080 $00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 6-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers. NOTE For M680, M1680, and M68HC0 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Freescale Semiconductor

33 FLASH Memory (FLASH).6 FLASH Memory (FLASH) This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. The FLASH memory consists of an array of 096 or 16 bytes with an additional 8 bytes for user vectors. The minimum size of FLASH memory that can be erased is 6 bytes; and the maximum size of FLASH memory that can be programmed in a program cycle is bytes (a row). Program and erase operations are facilitated through control bits in the FLASH control register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: $EE00 $FDFF; user memory, 096 bytes: MC68HC908QY and MC68HC908QT $F800 $FDFF; user memory, 16 bytes: MC68HC908QY, MC68HC908QT, MC68HC908QY1 and MC68HC908QT1 $FFD0 $FFFF; user interrupt vectors, 8 bytes. NOTE An erased bit reads as a 1 and a programmed bit reads as a 0. A security feature prevents viewing of the FLASH contents. (1).6.1 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: $FE08 Bit Bit 0 Read: Write: HVEN MASS ERASE PGM Reset: = Unimplemented Figure -. FLASH Control Register (FLCR) HVEN High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS Mass Erase Control Bit This read/write bit configures the memory for mass erase operation. 1 = Mass erase operation selected 0 = Mass erase operation unselected 1. No security feature is absolutely secure. However, Freescale s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor