system on chip architecture CONTENTS Processor : An Architectural View Simple Sequential Processor

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1 Contents i system on chip architecture FOR m.tech (jntu - h&k) i year Ii semester (COMMON TO EMBEDDED SYSTEMS, VLSI AND VLSI DESIGN) CONTENTS UNIT - I [CH. H. - 1] ] [INTRODUCTION TO THE SYSTEM APPROACH] SYSTEM ARCHITECTURE COMPONENTS OF THE SYSTEM HARDWARE AND SOFTWARE PROCESSOR ARCHITECTURES Processor : A Functional View Processor : An Architectural View Simple Sequential Processor Pipelined Processor Instruction-Level Parallelism (ILP) SIMD Architectures Array Processors Vector Processors Multiprocessors MEMORY AND ADDRESSING SOC Memory Examples Addressing : The Architecture of Memory Memory for SOC Operating System

2 ii Contents 1.6 SYSTEM LEVEL INTERCONNECTION Bus-Based Approach Network-onon-Chip Approach AN APPROACH FOR SOC DESIGN Requirements and Specifications Design Iteration SYSTEM ARCHITECTURE AND COMPLEXITY Short Questions and Answers Expected University Questions with Answers UNIT - II [CH. - 2] ] [PROCESSORS PROCESSORS] INTRODUCTION PROCESSOR SELECTION FOR SOC Overview Soft Processors Examples : Processor Core Selection Processor Core Selection : General Core Path ath Processor Core Selection : Compute Core Path ath BASIC CONCEPTS IN PROCESSOR ARCHITECTURE Instruction Set Some Instruction Set Conventions Branches Interrupts and Exceptions BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE BASIC ELEMENTS IN INSTRUCTION HANDLING The Instruction Decoder and Interlocks Bypassing Execution Unit

3 Contents iii 2.6 BUFFERS : MINIMIZING PIPELINE DELAYS YS Mean Request Rate Buffers Buffers Designed for a Fixed or Maximum Request Rate BRANCHES : REDUCING THE COST OF BRANCHES Branch Target Capture : Branch Target Buffers (BTBs) Branch Prediction Static Prediction Dynamic Prediction : Bimodal Dynamic Prediction : Bimodal Dynamic Prediction : Two wo-l -Level Adaptive Dynamic Prediction : Combined Methods MORE ROBUST PROCESSORS : VECTOR, VERY LONG INSTRUCTION WORD (VLIW) AND SUPERSCALAR VECTOR OR PROCESSORS AND VECTOR OR INSTRUCTION EXTENSIONS Vector Functional Units VLIW PROCESSORS SUPERSCALAR PROCESSORS Data Dependencies Detecting Instruction Concurrency A Simple Implementation Preserving State with Out-of-Order Execution Short Questions and Answers Expected University Questions with Answers UNIT - III [CH. - 3] ] [MEMORY DESIGN FOR SOC] INTRODUCTION OVERVIEW SOC External Memory : Flash SOC Internal Memory : Placement The Size of Memory

4 iv Contents 3.3 SCRATCHP CHPADS AND CACHE CHE MEMORY CACHE CHE ORGANIZATION CACHE CHE DATA WRITE POLICIES STRATEGIES TEGIES FOR LINE REPLACEMENT AT MISS TIME Fetching a Line Line Replacement Cache Environment : Effect of System, Transactions and Multiprogramming TYPES OF CACHE Split-I and D-Caches and the Effect of Code Density MULTILEVEL CACHES CHES Limits On Cache Array Size Evaluating Multilevel Caches Logical Inclusion VIRTU TUAL AL-TO-REAL -REAL TRANSLATION TION SOC (ON-DIE) MEMORY SYSTEM MODELS OF SIMPLE PROCESSOR-MEMORY INTERACTION Models of Multiple Simple Processors and Memory The Strecker-Ravi Model Interleaved Caches Short Questions and Answers Expected University Questions with Answers UNIT - IV [CH. - 4] ] [INTERCONNECT ] INTRODUCTION OVERVIEW : INTERCONNECT ARCHITECTURES BUS : BASIC ARCHITECTURE Arbitration and Protocols Bus Bridge Physical Bus Structure Bus Varieties

5 Contents v 4.4 SOC STAND ANDARD ARD BUSES AMBA Advanced High-Performance Bus (AHB) Advanced Peripheral Bus (APB) CoreConnect Processor Local Bus (PLB) On-Chip Peripheral Bus Device Control Register (DCR) Bus Bus Interface Units : Bus Sockets and Bus Wrappers ANALYTIC BUS MODELS Contention and Shared Bus Simple Bus Model : Without Resubmission Bus Model with Request Resubmission Using the Bus Model : Computing the Offered Occupancy Effect of Bus Transactions and Contention Time ime Short Questions and Answers Expected University Questions with Answers UNIT - IV [CH. - 5] ] [CUSTOMIZATION AND CONFIGURABILITY] SOC CUSTOMIZA OMIZATION : AN OVERVIEW CUSTOMIZING INSTRUCTION PROCESSORS Processor Customization Approaches Architecture Description Identifying Custom Instructions Automatically RECONFIGURABLE TECHNOLOGIES Reconfigurable Functional Units (FUs) Reconfigurable Interconnects Software Configurable Processors

6 vi Contents 5.4 MAPPING DESIGNS ONTO O RECONFIGURABLE DEVICES INSTANCE ANCE-SPECIFIC DESIGN CUSTOMIZABLE SOFT PROCESSOR : AN EXAMPLE RECONFIGURATION TION Reconfiguration Overhead Analysis Trade rade-off Analysis : Reconfigurable Parallelism Short Questions and Answers Expected University Questions with Answers UNIT - V [CH. H. - 6] ] [APPLICATION STUDIES/CASE STUDIES] SOC DESIGN APPROACH ADVANCED ANCED ENCRYPTION STAND ANDARD ARD (AES) Algorithm and Requirements Design and Evaluation IMAGE COMPRESSION JPEG Compression Short Questions and Answers Expected University Questions with Answers

anced computer architecture CONTENTS AND THE TASK OF THE COMPUTER DESIGNER The Task of the Computer Designer

anced computer architecture CONTENTS AND THE TASK OF THE COMPUTER DESIGNER The Task of the Computer Designer Contents advanced anced computer architecture i FOR m.tech (jntu - hyderabad & kakinada) i year i semester (COMMON TO ECE, DECE, DECS, VLSI & EMBEDDED SYSTEMS) CONTENTS UNIT - I [CH. H. - 1] ] [FUNDAMENTALS