74LVXC Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs

Transcription

1 74LXC Bit Dual Supply Configurable oltage Interface Traceiver with 3-STATE Outputs Features Bidirectional interface between 3 and 3-to-5 buses Control inputs compatible with TTL level Outputs source/sink up to 24 ma Guaranteed simultaneous switching noise level and dynamic threshold performance Implements proprietary EMI reduction circuitry Flexible CCB operating range Allows B Port and CCB to float simultaneously when OE is HIGH Functionally compatible with the 74 series 245 Ordering Code: General Description February 2009 The LXC3245 is a 24-pin dual-supply, 8-bit configurable voltage interface traceiver suited for PCMCIA and other real time configurable I/O applicatio. The CCA pin accepts a 3 supply level. The A Port is a dedicated 3 port. The CCB pin accepts a 3-to-5 supply level. The B Port is configured to track the CCB supply level respectively. A 5 level on the CC pin will configure the I/O pi at a 5 level and a 3 CC will configure the I/O pi at a 3 level. The A Port should interface with a 3 host system and the B Port to the card slots. This device will allow the CCB voltage source pin and I/O pi on the B Port to float when OE is HIGH. This feature is necessary to buffer data to and from a PCMCIA socket that permits PCMCIA cards to be ierted and removed during normal operation. Order Number Package Number Package Description 74LXC3245WM M24B 224-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LXC3245QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 74LXC3245MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Logic Symbol/s Pin Descriptio Pin Names OE T/R A 0 A 7 B 0 B 7 Output Enable Input Description Tramit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs Connection Diagram/s 74LXC Bit Dual Supply Configurable oltage Interface Traceiver with 3-STATE Outputs 1994 Fairchild Semiconductor Corporation

2 Truth Table/s H = HIGH oltage Level L = LOW oltage Level X = Immaterial Logic Diagram/s Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State 74LXC Bit Dual Supply Configurable oltage Interface Traceiver with 3-STATE Outputs 2

3 Absolute Maximum Ratings(Note 1) Supply oltage ( CCA, CCB ) 0.5 to +7.0 DC Input oltage ( I OE, T/R 0.5 to CCA +0.5 DC Input/Output oltage ( I/O A n 0.5 to CCA B n 0.5 to CCB +0.5 DC Input Diode Current (I IK OE, T/R ±20 ma DC Output Diode (I OK ) Current ±50 ma DC Output Source or Sink Current (I O ) ±50 ma DC CC or Ground Current per Output Pin (I CC or I GND ) ±50 ma and Max Current ±200 ma Storage Temperature Range (T STG ) 65 C to +150 C DC Latch-Up Source or Sink Current ±300 ma DC Electrical Characteristics Recommended Operating Conditio (Note 2) Supply oltage CCA 2.7 to 3.6 CCB 3.0 to 5.5 Input oltage ( I OE, T/R 0 to CCA Input Output oltage ( I/O A n 0 to B n 0 to CCB Free Air Operating Temperature (T A ) 40 C to +85 C Minimum Input Edge Rate (Δt/Δ) 8 / IN from 30% to 70% of CC 3.0, 4.5, 5.5 Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditio table will define the conditio for actual device operation. Note 2: The A Port unused pi (inputs or I/Os) must be held HIGH or LOW. They may not float. CCA CCB T A = 25 C T A = 40 C to +85 C Symbol Parameter Units Conditio () () Typ Guaranteed Limits IHA Minimum HIGH A n, OUT 0.1 Level Input OE or oltage T/R CC 0.1 IHB B n ILA Maximum LOW A n, OUT 0.1 Level Input OE or oltage T/R CC 0.1 ILB B n OHA Minimum HIGH Level I OUT = 100 μa Output oltage I OH = 12 ma I OH = 24 ma I OH = 12 ma I OH = 24 ma OHB I OUT = 100 μa I OH = 12 ma I OH = 24 ma I OH = 24 ma OLA Maximum LOW Level I OUT = 100 μa Output oltage I OL = 24 ma I OL = 12 ma I OL = 24 ma OLB I OUT = 100 μa I OL = 24 ma I OL = 24 ma I IN Maximum Input ±0.1 ±1.0 I = CCA, GND Leakage ±0.1 ±1.0 μa OE, T/R 74LXC Bit Dual Supply Configurable oltage Interface Traceiver with 3-STATE Outputs 3

4 74LXC3245 DC Electrical Characteristics (Continued) CCA CCB T A = 25 C T A = 40 C to +85 C Symbol Parameter Units Conditio () () Typ Guaranteed Limits I OZA Maximum 3-STATE ±0.5 ±5.0 I = IL, IH, Output Leakage ±0.5 ±5.0 µa OE = A n O = CCA, GND I OZB Maximum 3-STATE ±0.5 ±5.0 I = IL, IH, Output Leakage ±0.5 ±5.0 µa OE = B n O = CCB, GND I CC Maximum B n I = CCB 2.1 ma I CC /Input All Inputs I = CC 0.6 I CCA1 Quiescent CCA A n = CCA or GND Supply Current 3.6 Open 5 50 µa B n = Open, OE = CCA, as B Port Floats T/R = CCA, CCB = Open I CCA2 Quiescent CCA A n = CCA or GND, Supply Current µa B n = CCB or GND, OE = GND, T/R = GND I CCB Quiescent CCB A n = CCA or GND, Supply Current µa B n = CCB or GND, OLPA Quiet Output Maximum Dynamic OLPB OL OLA Quiet Output Minimum Dynamic OLB OL IHDA Minimum HIGH Level Dynamic IHDB Input oltage ILDA Maximum LOW Level Dynamic ILDB Input oltage Note 3: Worst case package. Note 4: Max number of outputs defined as (n). Data inputs are driven 0 to CC level; one output at GND. Note 5: Max number of Data Inputs (n) switching. (n 1) inputs switching 0 to CC level. Input-under-test switching: CC level to threshold ( IHD ), 0 to threshold ( ILD ), f = 1 MHz. OE = GND, T/R = CCA (Note 3)(Note 4) (Note 3)(Note 4) (Note 3)(Note 4) (Note 3)(Note 4) (Note 3)(Note 5) (Note 3)(Note 5) (Note 3)(Note 5) (Note 3)(Note 5) 4

5 AC Electrical Characteristics T A = +25 C T A = 40 C to +85 C T A = +25 C T A = 40 C to +85 C C L = 50 pf C L = 50 pf C L = 50 pf C L = 50 pf Symbol Parameter CCA = CCA = CCA = CCA = CCB = CCB = CCB = CCB = Units 74LXC3245 Min Typ Max Min Max Min Typ Max Min Max (Note 6) (Note 7) t PHL Propagation Delay t PLH A to B t PHL Propagation Delay t PLH B to A t PZL Output Enable Time t PZH OE to B t PZL Output Enable Time t PZH OE to A t PHZ Output Disable Time t PLZ OE to B t PHZ Output Disable Time t PLZ OE to A t OSHL Output to Output t OSLH Skew (Note 8) Data to Output Note 6: Typical values at CCA = 3.3, CCB = 25 C. Note 7: Typical values at CCA = 3.3, CCB = 25 C. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ). Parameter guaranteed by design. Capacitance Symbol Parameter Typ Units Conditio C IN Input Capacitance 4.5 pf CC = Open C I/O Input/Output Capacitance 10 pf CCA = 3.3 CCB = 5.0 C PD Power Dissipation A B 50 pf CCB = 5.0 Capacitance (Note 9) B A 40 pf CCA = 3.3 Note 9: C PD is measured at 10 MHz. 5

6 74LXC3245 Power Up Coideratio To iure the system does not experience unnecessary I CC current draw, bus contention, or oscillatio during power up, the following guidelines should be adhered to (refer to Table 1): Power up the control side of the device first. This is the CCA side. OE should ramp with or ahead of CCA. This will help guard agait bus contention. The Tramit/Receive control pin (T/R) should ramp with CCA, this will eure that the A Port data pi are configured as inputs. With CCA receiving power first, the A I/O Port should be configured as inputs to help guard agait bus contention and oscillatio. A side data inputs should be driven to a valid logic level. This will prevent excessive current draw. The above steps will eure that no bus contention or oscillatio, and therefore no excessive current draw occurs during the power up cycling of these devices. These steps will help prevent possible damage to the tralator devices and potential damage to other system components. TABLE 1. Low oltage Tralator Power Up Sequencing Table Device Type CCA CCB T/R OE A Side I/O B Side I/O 74LXC3245 Please reference Application Note AN-5001 for more detailed information on using Fairchild s LX Low oltage Dual Supply CMOS Tralating Traceivers. Configurable I/O Application for PCMCIA Cards Block Diagram Floatable Pin Allowed 3 3 to 5.5 ramp ramp logic yes, CCB and B outputs (power up 1st) configurable with CCA with CCA 0 or CCA I/O s w/ OE HIGH The LXC3245 is a 24-pin dual supply device well suited for PCMCIA configurable I/O applicatio. Ideal for low power notebook desig, the LXC3245 coumes less than 1 mw of quiescent power in all modes of operation. The LXC3245 meets all PCMCIA I/O voltage requirements at 5 and 3.3 operation. By tying CCB of the LXC3245 to the card voltage supply, the PCMCIA card will always experience rail to rail output swings, maximizing the reliability of the interface. The CCA pin on the LXC3245 must always be tied to a 3 power supply. This voltage connection provides internal references needed to account for variatio in CCB. When connected as in the figure above, the LXC3245 meets all the voltage and current requirements of the ISA bus standard (IEEE P996). 6

7 Physical Dimeio inches (millimeters) unless otherwise noted 74LXC Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA24 7

8 74LXC Bit Dual Supply Configurable oltage Interface Traceiver with 3-STATE Outputs Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

9 9 74LXC Bit Dual Supply Configurable oltage Interface Traceiver with 3-STATE Outputs