N U M B ER O F V L V C C T R A N SL A T O R S

Transcription

1 ; Rev 2; 12/ to +3.6,.1µA, 1Mbps, General Description The 8-channel level translator provides the level shifting necessary to allow 1Mbps data transfer in a multivoltage system. Externally applied voltages, and, set the logic levels on either side of the device. Logic signals present on the L side of the device appear as a higher voltage logic signal on the side of the device, and vice-versa. The features an input that, when at logic low, places all inputs/outputs on both sides in tristate and reduces the CC and supply currents to.1µa. This device operates at a guaranteed data rate of 1Mbps for > 1.8. The accepts a CC voltage from to +3.6 and a L voltage from +1.2 to (CC -.4), making it ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The is available in 5 x 4 UCSP, 2-pin 5mm x 5mm QFN, and 2-pin TSSOP packages. Applications Low-oltage ASIC Level Translation Cell Phones SPI, MICROWIRE Level Translation Portable POS Systems Portable Communication Devices GPS Telecommunications Equipment Features 1Mbps Guaranteed Data Rate Bidirectional Level Translation L Operation Down to +1.2 Ultra-Low.1µA Supply Current in Shutdown Low-Quiescent Current (.1µA) UCSP, QFN, and TSSOP Packages Pin Configurations TOP IEW I/O I/O 1 I/O I/O 2 I/O I/O 3 I/O I/O GND I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 TSSOP Pin Configurations continued at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Typical Operating Circuit appears at end of data sheet. Ordering Information PART TEMP RANGE PIN-PACKAGE N U M B ER O F C C T R A N SL A T O R S NUMBER OF TRANSLATORS DATA RATE (Mbps) EUP -4 C to +85 C 2 TSSOP EBP-T -4 C to +85 C 5 x 4 UCSP EGP -4 C to +85 C 2 QFN-EP* *EP = Exposed paddle. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) to to +4 I/O to ( +.3) I/O to ( +.3) to ( +.3) Short-Circuit Duration I/O, I/O to GND...Continuous Continuous Power Dissipation (T A = +7 C) 2-Pin TSSOP (derate 11mW/ C above +7 C)...879mW 5 x 4 UCSP (derate 1mW/ C above +7 C)...8mW 2-Pin QFN (derate 2.mW/ C above +7 C)...1.6W Operating Temperature Range...-4 C to +85 C Junction Temperature C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( = to +3.6, = +1.2 to ( -.4) (Note 1), =, C IOL 15pF, C IOCC 4pF, T A = T MIN to T MAX. Typical values are at = +3.3, = +1.8, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Supply Range 1.2 Supply Range Supply Current from I QCC I/O _ =, I/O _ = or I/O _ =, I/O _ =.1 1 µa I/O _ =, I/O _ = or I/O _ =, I/O _ =.1 4 Supply Current from I QL I/O _ =, I/O _ = or I/O _ =, I/O _ =, < Tristate Output Mode Supply Current Tristate Output Mode Supply Current -.4 I TS-CC T A = +25 C, =.3 1 µa T A = +25 C, =.1.2 I TS-L T A = +25 C, =, = I/O Tristate Output Mode T A = +25 C, =,.15 Leakage Current T A = +25 C, =, = LOGIC-LEEL THRESHOLDS I/O _ Input-oltage High IHL 2/3 x I/O _ Input-oltage Low ILL 1/3 x I/O _ Input-oltage High IHC 2/3 x I/O _ Input-oltage Low ILC 1/3 x Input-oltage High IH T A = +25 C 2/3 x µa µa µa 2

3 ELECTRICAL CHARACTERISTICS (continued) ( = to +3.6, = +1.2 to ( -.4) (Note 1), =, C IOL 15pF, C IOCC 4pF, T A = T MIN to T MAX. Typical values are at = +3.3, = +1.8, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input-oltage Low IL T A = +25 C 1/3 x Input Current T A = +25 C ±5 µa I/O _ Output-oltage High OHL I/O _ source current = 2µA 2/3 x I/O _ Output-oltage Low OLL I/O _ sink current = 2µA 1/3 x I/O _ Output-oltage High OHC I/O _ source current = 2µA 2/3 x I/O _ Output-oltage Low OLC I/O _ sink current = 2µA 1/3 x TIMING CHARACTERISTICS ( = to +3.6, = +1.2 to ( -.4) (Note 1), =, C IOL 15pF, C IOCC 4pF, T A = T MIN to T MAX. Typical values are at = +3.3, = +1.8, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS C IO C C = 15p F, Fi g ur e I/O _ Rise Time t RCC C IO C C = 2p F, Fi g ur e 1 3 C IO C C = 4p F, Fi g ur e 1 4 ns C IO C C = 15p F, Fi g ur e I/O _ Fall Time t FCC C IO C C = 2p F, Fi g ur e 1 3 C IO C C = 4p F, Fi g ur e 1 4 ns I/O _ One-Shot Output 18.5 Ω I/O _ Rise Time t RL C IOL = 15pF, Figure ns I/O _ Fall Time t FL C IOL = 15pF, Figure ns I/O _ One-Shot Output Impedance 12.5 Ω Propagation Delay (Driving I/O _ ) I/O L-CC C IO C C = 15p F, Fi g ur e ns 3

4 TIMING CHARACTERISTICS (continued) ( = to +3.6, = +1.2 to ( -.4) (Note 1), =, C IOL 15pF, C IOCC 4pF, T A = T MIN to T MAX. Typical values are at = +3.3, = +1.8, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Propagation Delay (Driving I/O _ ) I/O CC-L C IOL = 15p F, Fi g ur e 2 6 ns Part-to-Part Skew t PPSKEW C IO C C = 15p F, C IOL = 15p F, C C = 2.5, = 1.8 ( N ote 3) 4 ns Propagation Delay from I/O _ to I/O _ after Propagation Delay from I/O _ to I/O _ after t -CC C IO C C = 15p F, Fi g ur e 3 1 ns t -L C IOL = 15p F, Fi g ur e 4 1 ns Maximum Data Rate C IO C C = 15p F, C IOL = 15p F, > C IO C C = 15p F, C IOL = 15p F, > Mbps Note 1: must be less than or equal to -.4 during normal operation. However, can be greater than -.4 during starting up and shutting down conditions. Note 2: All units are 1% production tested at T A = +25 C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 3: Not production tested. Guaranteed by design. Typical Operating Characteristics (Data rate = 1Mbps, = 3.3, = 1.8, T A = +25 C, unless otherwise noted.) L SUPPLY CURRT (ma) SUPPLY CURRT vs. SUPPLY OLTAGE.2 DRIING I/O = 1.8 C IOCC = 15pF SUPPLY OLTAGE () toc1 L SUPPLY CURRT (ma) SUPPLY CURRT vs. SUPPLY OLTAGE DRIING I/O.1 L = 1.25 C IOCC = 15pF SUPPLY OLTAGE () toc2 CC SUPPLY CURRT (ma) SUPPLY CURRT vs. SUPPLY OLTAGE 5 DRIING I/O = 1.8 C IOCC = 15pF SUPPLY OLTAGE () toc3 4

5 Typical Operating Characteristics (continued) (Data rate = 1Mbps, = 3.3, = 1.8, T A = +25 C, unless otherwise noted.) CC SUPPLY CURRT (ma) SUPPLY CURRT vs. SUPPLY OLTAGE 5 DRIING I/O = 1.25 C IOCC = 15pF SUPPLY OLTAGE () toc4 L SUPPLY CURRT (ma) SUPPLY CURRT vs. TEMPERATURE 2.4 DRIING I/O C IOL = 15pF TEMPERATURE ( C) toc5 CC SUPPLY CURRT (ma) SUPPLY CURRT vs. TEMPERATURE DRIING I/O C IOL = 15pF TEMPERATURE ( C) toc6 L SUPPLY CURRT (ma) SUPPLY CURRT vs. CAPACITIE LOAD ON I/O toc7 CC SUPPLY CURRT (ma) SUPPLY CURRT vs. CAPACITIE LOAD ON I/O toc8 RISE/FALL TIME (ns) RISE/FALL TIME vs. CAPACITIE LOAD ON I/O t RISE t FALL toc9 DRIING I/O CAPACITIE LOAD (pf) DRIING I/O CAPACITIE LOAD (pf) DRIING I/O CAPACITIE LOAD (pf) 5

6 Typical Operating Characteristics (continued) (Data rate = 1Mbps, = 3.3, = 1.8, T A = +25 C, unless otherwise noted.) RISE/FALL TIME (ns) RISE/FALL TIME vs. CAPACITIE LOAD ON I/O t RISE t FALL DRIING I/O CAPACITIE LOAD (pf) toc1 PROPAGATION DELAY (ns) PROPAGATION DELAY vs. CAPACITIE LOAD ON I/O t PLH t PHL DRIING I/O CAPACITIE LOAD (pf) toc11 PROPAGATION DELAY (ns) PROPAGATION DELAY vs. CAPACITIE LOAD ON I/O t PLH t PHL DRIING I/O CAPACITIE LOAD (pf) toc12 TYPICAL I/O DRIING toc t -CC vs. TEMPERATURE (C IOCC = 15pF) toc t -L vs. TEMPERATURE (C IOL = 15pF) toc15 I/O 1/div I/O 1/div t-cc (ns) t-l (ns) ns/div TEMPERATURE ( C) TEMPERATURE ( C) 6

7 Pin Description PIN BUMP TSSOP QFN UCSP NAME FUNCTION 1 18 B1 I/O 1 Input/Output 1, Referenced to 2 19 A1 I/O 2 Input/Output 2, Referenced to 3 2 B2 I/O 3 Input/Output 3, Referenced to 4 1 A2 I/O 4 Input/Output 4, Referenced to 5 2 A3 Input oltage, +1.2 ( -.4). Bypass to GND with a.1µf capacitor. 6 3 A4 Enable Input. If is pulled low, all inputs/outputs are in tristate. Drive high ( ) for normal operation. 7 4 B3 I/O 5 Input/Output 5, Referenced to 8 5 A5 I/O 6 Input/Output 6, Referenced to 9 6 B4 I/O 7 Input/Output 7, Referenced to 1 7 B5 I/O 8 Input/Output 7, Referenced to 11 8 C5 I/O 8 Input/Output 8, Referenced to 12 9 C4 I/O 7 Input/Output 7, Referenced to 13 1 D5 I/O 6 Input/Output 6, Referenced to C3 I/O 5 Input/Output 5, Referenced to D4 GND Ground D3 Input oltage, Bypass to GND with a.1µf capacitor D2 I/O 4 Input/Output 4, Referenced to C2 I/O 3 Input/Output 3, Referenced to D1 I/O 2 Input/Output 2, Referenced to 2 17 C1 I/O 1 Input/Output 1, Referenced to 7

8 I/O Test Circuits/Timing Diagrams I/O C IOCC SOURCE t RISE/FALL 3ns I/O 9% 5% 1% I/O L-CC I/O L-CC I/O 9% 5% 1% t FCC t RCC Figure 1. Driving I/O Test Circuit and Timing 8

9 I/O C IOL Test Circuits/Timing Diagrams (continued) I/O SOURCE t RISE/FALL 3ns I/O 9% 5% 1% I/O CC-L I/O CC-L I/O 9% 5% 1% t FL t RL Figure 2. Driving I/O Test Circuit and Timing 9

10 SOURCE I/O Test Circuits/Timing Diagrams (continued) t' -CC I/O I/O C IOCC I/O /2 SOURCE t" -CC I/O I/O I/O C IOCC I/O CC /2 Figure 3. Propagation Delay from I/O to I/O after t -CC IS WHICHEER IS LARGER BETWE t' -CC AND t" -CC. SOURCE t' -L I/O I/O I/O C IOL I/O /2 SOURCE t" -L I/O I/O I/O C IOL I/O /2 Figure 4. Propagation Delay from I/O to I/O after t -CC IS WHICHEER IS LARGER BETWE t' -CC AND t" -CC. 1

11 Detailed Description The logic-level translator provides the level shifting necessary to allow 1Mbps data transfer in a multivoltage system. Externally applied voltages, CC and, set the logic levels on either side of the device. Logic signals present on the L side of the device appear as a higher voltage logic signal on the side of the device, and vice-versa. The bidirectional level translator allows data translation in either direction ( ) on any single data line. The accepts from +1.2 to (CC -.4) and operate with from to +3.6, making it ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. I 15Ω P ONE-SHOT N ONE-SHOT 4kΩ O The features an input enable mode () that reduces CC and L supply currents to.1µa, when in tristate mode. This device operates at a guaranteed data rate of 1Mbps for > TYPICAL DRIING ONE-CHANNEL ON SIDE Level Translation For proper operation, ensure that , +1.2 ( -.4). During power-up sequencing, L does not damage the device. During powersupply sequencing, when is floating and is powering up, up to 4mA current can be sourced to each load on the side, yet the device does not latch up. The maximum data rate depends heavily on the load capacitance (see the Typical Operating Characteristics, Rise/Fall Times), output impedance of the driver, and the operating voltage range (see the Timing Characteristics). Input Driver Requirements The architecture is based on a one-shot accelerator output stage (see Figure 5). Accelerator output stages are always in tristate mode except when there is a transition on any of the translators on the input side, either I/O L or I/O. Then, a short pulse is generated during which the accelerator output stages become active and charge/discharge the capacitances at the I/Os. Due to its bidirectional nature, both input stages become active during the one-shot pulse. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps to speed up the transition on the driven side. For proper operation, the external driver must meet the following conditions: <25Ω output impedance and >2mA output current. Figure 6 shows a graph of Typical Input Current vs. Input oltage. O 15Ω P ONE-SHOT N ONE-SHOT TYPICAL DRIING ONE-CHANNEL ON SIDE Output Load Requirements The I/O was designed to drive CMOS inputs. Do not load the I/O lines with a resistive load less than 25kΩ. Also, do not place an RC circuit at the input of the to slow down the edges. If a slower data rate is required, please see the MAX3E/MAX31E logic-level translator. For I 2 C level translation, please refer to the MAX3372E MAX3379E/MAX339E MAX3393E data sheet. 4kΩ Figure 5. Simplified Diagram (1 I/O line) I 11

12 TH_IN /R IN * -( S - TH_IN )/R IN * I IN *R IN = 4kΩ WH DRIING SIDE. R IN = 15Ω WH DRIING SIDE. Figure 6. Typical I IN vs. IN TH_IN Enable Input () The features an input. Pull low to set the I/O on both sides in tristate output mode. Drive to logic high ( ) for normal operation. Applications Information Power-Supply Decoupling To reduce ripple and the chance of introducing data errors, bypass L and CC to ground with a.1µf ceramic capacitor. Place the bypass capacitors as close to the power-supply input pins as possible. 8-Bit Bus Translation The level-shifts the data present on the I/O line between +1.2 to +3.6, making it ideal for level translation between a low-voltage ASIC and a higher voltage system. The Typical Operating Circuit shows the bidirectional translator in an 8-bit bus level translation from a 1.8 system to a 3.3 system and vice versa. Unidirectional vs. Bidirectional Level Translator The bidirectional translator can operate as a unidirectional device to translate signals without inversion. This device provides the smallest solution (UCSP package) for unidirectional level translation without inversion. S IN WHERE S = OR SYSTEM CONTROLLER BIT BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7.1µF Typical Operating Circuit I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 GND I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8.1µF BIT BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT SYSTEM

13 TOP IEW I/O I/O L3 19 I/O L2 18 I/O L1 17 I/O CC1 16 I/O CC2 15 I/O 3 D Pin Configurations (continued) I/O 2 I/O 4 GND I/O 6 I/O 5 I/O **EXPOSED PADDLE I/O 4 CC GND I/O 5 C B I/O 1 I/O 3 I/O 5 I/O 7 I/O 1 I/O 3 I/O 5 I/O 7 I/O 8 I/O A I/O 2 I/O 4 I/O 6 I/O L7 I/O L8 I/O CC8 I/O CC7 I/O CC6 5mm x 5mm QFN 2 UCSP (BOTTOM IEW) Chip Information TRANSISTOR COUNT: 1447 PROCESS: BiCMOS 13

14 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to TSSOP4.4mm.EPS 14

15 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to 5x4 UCSP.EPS PACKAGE OUTLINE, 5x4 UCSP I

16 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to 32L QFN.EPS 16

17 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.