LCDD Application Note

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Amice Randall
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1 Feature: LCDD Application Note SM79108 incorporates an on-chip LCD driver which generates and common signals output according to the display data saved in registers (0E1H~0E7H) and incorporates and

1 1 Feature: LCDD Application Note SM79108 incorporates an on-chip LCD driver which generates and common signals output according to the display data saved in registers (0E1H~0E7H) and incorporates and common driver which can drive the LCD panel directly The on chip LCD driver has the following features: 1.1 1/4 duty (time multiplexing by 4) and 1/3 bias LCD segment driver mA operation current (1.2uA in power down mode) bits of display data buffer segment driver and 4 common driver output 1.5 A frame frequency can be selected 2 LCDD Function use SFR: Mnemonic Description Direct Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET LCDD LCDCON LCD control register DFh LCD_ON LCD_EN SEG Unused Unused LS2 LS1 LS0 00h LCDB0 Registers 0 E1h SEG0 SEG0 SEG0 SEG0 SEG1 SEG1 SEG1 SEG1 00h LCDB1 Registers 1 E2h SEG2 SEG2 SEG2 SEG2 SEG3 SEG3 SEG3 SEG3 00h LCDB2 Registers 2 E3h SEG4 SEG4 SEG4 SEG4 SEG5 SEG5 SEG5 SEG5 00h LCDB3 Registers 3 E4h SEG6 SEG6 SEG6 SEG6 SEG7 SEG7 SEG7 SEG7 00h LCDB4 Registers 4 E5h SEG8 SEG8 SEG8 SEG8 SEG9 SEG9 SEG9 SEG9 00h LCDB5 Registers 5 E6h SEG10 SEG10 SEG10 SEG10 SEG11 SEG11 SEG11 SEG11 00h LCDB6 Registers 6 E7h SEG12 SEG12 SEG12 SEG12 SEG13 SEG13 SEG13 SEG13 00h P0CON P0 Control Register 9Ah SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 00h P2CON P2 Control Register 9Ch SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 00h IRFWX-A119 1 Ver. A 2009/02

2 Mnemonic: LCDCON Address: DFh LCD_ON LCD_EN SEG Unused Unused LS2 LS1 LS0 00h LCD_ON: LCD display bit. = 1: LCD display ON = 0: LCD display OFF LCD_EN: LCD enable bit. SEG: #PSEN and ALE switch to SEG4 and SEG5 control bit. = 1: enable the LCD function on pin #PSEN/SEG4 and ALE/SEG5 = 0: no operation F LS[2:0]: Frequency pre-scaler select,determine the clock frequency of LCD driver, Fclk_lcd LS2 LS1 LS0 Pre-scaler Select The clock frequency of LCD driver is obtained using the following formula: Fclk_lcd = {[Fosc/2] 32 x Pre-scaler} The frame of LCD driver is determined as follows: Frame = Fclk_lcd/256 The typical range of Frame is: 1026Hz ~ 8 Hz (depend on different LCD panel) Different LCD panel have different material parameter So user must to select appropriate value of Pre-scaler that can get more clear display condition IRFWX-A119 2 Ver. A 2009/02

3 Addressing Map of the registers is shown as follows: Com3 Com2 Com1 Com0 Com3 Com2 Com1 Com0 Mnemonic Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDB0 E1H SEG0 SEG0 SEG0 SEG0 SEG1 SEG1 SEG1 SEG1 LCDB1 E2H SEG2 SEG2 SEG2 SEG2 SEG3 SEG3 SEG3 SEG3 LCDB2 E3H SEG4 SEG4 SEG4 SEG4 SEG5 SEG5 SEG5 SEG5 LCDB3 E4H SEG6 SEG6 SEG6 SEG6 SEG7 SEG7 SEG7 SEG7 LCDB4 E5H SEG8 SEG8 SEG8 SEG8 SEG9 SEG9 SEG9 SEG9 LCDB5 E6H SEG10 SEG10 SEG10 SEG10 SEG11 SEG11 SEG11 SEG11 LCDB6 E7H SEG12 SEG12 SEG12 SEG12 SEG13 SEG13 SEG13 SEG13 3 The output control of Segment and Commons Mnemonic: P0CON Address: 9Ah SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 00h P0CON[7:0]: P0 Control Register. = 1: enable I/O ports(p0[7:0]) for Seg[6:13] output = 0: P0 as normal I/O port Mnemonic: P2CON Address: 9Ch SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 00h P2CON[7:0]: P2 Control Register. = 1: enable I/O ports(p2[7:0]) Seg[3:0] and Com[3:0] output = 0: P2 as normal I/O port Port 2 Configuration Register (P2CON) control Com0 ~ Com3 and Seg0 ~ Seg3 outputport 0 Configuration Register (P0CON) control Seg6 ~ Seg13 output And the Bit-5 of LCDCON register control the Seg4 / Seg5 output, like below code description MOV LCDCON, #0E0H LCD_ON(Bit-7) = 1, display on LCD_EN (Bit-6)= 1, enable LCD SEG = 1(Bit-5), I/O ports are ALE and #PSEN for seg5 and seg4 output LS[2:0]=000, frequency pre-scaler select Fclk_lcd = Fosc/64 MOV P0CON, #0FFH enable I/O ports(p0[7:0]) for Seg[6:13] output MOV P2CON, #0FFH enable I/O ports(p2[7:0]) for Seg[3:0] and Com[3:0] output IRFWX-A119 3 Ver. A 2009/02

4 4 Sample program: ORG 0000H START: MOV P0CON, #0FFH MOV P2CON, #0FFH MOV LCDCON, #0C0H Go: MOV LCDB0, #80H 0 = 1000_0000 MOV LCDB1, #08H 1 = 0000_1000 MOV LCDB2, #42H 2 = 0100_0010 MOV LCDB3, #0AAH 3 = 1010_1010 MOV LCDB4, #52H 4 = 0101_0010 MOV LCDB5, #F3H 5 = 1111_0011 MOV LCDB6, #16H 6 = 0001_0110 CALL Delay JMP START Delay: MOV R1,#7 in1: MOV R2,#0 in2: MOV R3,#0 DJNZ R3,$ DJNZ R2,in2 DJNZ R1,in1 RET END COM3 COM2 COM1 COM0 SEG0 ON OFF OFF OFF SEG1 OFF OFF OFF OFF SEG2 OFF OFF OFF OFF SEG3 ON OFF OFF OFF SEG4 OFF ON OFF OFF SEG5 OFF OFF ON OFF SEG6 ON OFF ON OFF SEG7 ON OFF ON OFF SEG8 OFF ON OFF ON SEG9 OFF OFF ON OFF SEG10 ON ON ON ON SEG11 OFF OFF ON ON SEG12 OFF OFF OFF ON SEG13 OFF ON ON OFF IRFWX-A119 4 Ver. A 2009/02

5 5 Attention: 5.1 The instruction of Clear bit(example CLR P1.0) Complement bit(example CPL P1.0) and Set bit(example SETB P1.0)can not follow the instruction of LCD Buffer control,that will make the LCD display error For Example:(This sample program will make the LCD display error) MOV LCDB3,#80H CLR P The Logical-AND Logical Exclusive-OR and Logical-OR can be used to replace the CLR CPL and SETB or call a small delay loop For Example:(Use Logic instruction to replace the bit instruction) MOV ANL LCDB3,#80H P1,# B For Example:(Use a small delay loop between the instruction of LCD Buffer control and the bit control instruction) MOV LCDB3,#80H CALL Delay CLR P1.0 Delay: MOV DJNZ RET R1,#01h R1,$ IRFWX-A119 5 Ver. A 2009/02

Chapter 3. Bit Addressable Area. By DeccanRobots

Chapter 3. Bit Addressable Area. By DeccanRobots Chapter 3 Bit Addressable Area By DeccanRobots What is Bit Addressable Area? FFh 2Fh 20h 00h Data Memory General purpose Memory Area Bit Addressable Memory Registers Memory Area from 20H to 2FH is Bit