Performance of PC Solid-State Disks

Transcription

1 Universit of Marland ISCA 9 June 29 Performance of PC Solid-State Disks 1 as a Function of Bandwidth, Concurrenc, Device Architecture, and Sstem Organization & Bruce Jacob Electrical & Computer Engineering Universit of Marland at College Park cdirik@umd.edu

2 SOLID-STATE DISKS, Universit of Marland SSD Design is NOT Simple! Rotating Disks SSDs Rotating Disks vs.vs. SSDs Main take-awas take-awas Simple interface - no mechanics Main ISCA 9 June 29 Disk Disk Load / Load / Unload Unload Mechanism 2 Spindle & Motor Spindle & Motor Actuator Actuator Magnet structure of voice coil motor Coil Motor Memor Arras Memor Arras NoForget in-place updateou of data everthing ou knew about Forget everthing knew about rotating disks. SSDs different rotating disks. SSDs areare different Asmmetric read and write + erase time SSDs are complex software sstems SSDs are complex software sstems One doesn t One size doesn t fit fit all all Lack ofsize models (a) HDD Timing/performance Power (b) SSD

3 Universit of Marland ISCA 9 June 29 SSD Design is NOT Simple! Concurrenc Sstem- & device-level Architecture Host x16 Ctrl IDE ATA SCSI Host I/F Laer x2 SRAM MPU ECC Data & Ctrl Data Buffer x2 Translation Laer Controller x16 x16 NAND I/F Laer Arra Arra Arra Arra I/O bandwidth utilization Proprietar firmware FTL and/or Controller Mapping algorithms, wear leveling, garbage collection, ECC, request interleaving, write scheduling/striping Workload sensitive

4 Universit of Marland ISCA 9 June 29 4 Host x16 Modeling SSDs Ctrl IDE ATA SCSI Host I/F Laer x2 SRAM MPU ECC Data & Ctrl Data Buffer x2 Translation Laer Controller x16 x16 NAND I/F Laer Arra Arra Arra Arra 2 KB Page 128 KB Block 2 μs page read 2 μs page program ms block erase 2 GB total storage CE# W# R# I/O I/O Control Control Logic Addr Reg Status Reg Cmd Reg Row Column Arra Data Reg Cache Reg 2K btes Data Reg Cache Reg 1 Block 1 Page = 2 K btes 1 Blk = 64 Pages 124 Blocks per Device (1 Gb) Memor Bank

5 Modeling SSDs Universit of Marland ISCA 9 June 29 Read 8 KB (4 Pages) Read page from memor arra into data register R/W I/O [7:] Cmd Addr ccles.2 us Xfer from data to cache register 2 us us Rd Rd1 Rd2 Rd 248 ccles us Xfer from cache to data register us Subsequent page is accessed while data is read out from cache register DO DO1 DO2 DO 2 us Page is programmed while data for subsequent page is written into cache register Write 8 KB (4 Pages) R/W I/O [7:] Cmd Pr Pr1 Pr2 Pr Addr DI DI1 DI2 DI ccles.2 us 248 ccles us CE# W# R# I/O I/O Control Control Logic Addr Reg Status Reg Cmd Reg Memor Bank Row Column Arra Data Reg Cache Reg 2K btes Data Reg Cache Reg 1 Block 1 Page = 2 K btes 1 Blk = 64 Pages 124 Blocks per Device (1 Gb)

6 Universit of Marland SSD Simulator Based on DiskSim v2. [Ganger99] ISCA 9 June 29 6 Device Driver Queue Scheduler Bus Controller Cache Queue Scheduler Bus Disk Cache Queue Scheduler Buffer R/W Heads Tracks Disk Platters Device Driver Queue Scheduler Bus Controller Cache Queue Scheduler LBA-PBA Table Free Block Table Controller Bus Interconnect Network Memor Arras

7 PC User Workloads Universit of Marland ISCA 9 June GB Request LBN Distribution Logical LBN (GB) Addr. 16 Space 8 Write Read Trace 1 Trace % 4% % 2% 1% Request Size Distribution 4 KB RIAL version 8 KB Large writes Write Read Trace 7 Trace Time (min) Time (min) % [, 2) [2, 4) Trace Duration (minutes) [4, 8) [8, 16) Avg. Number of I/O per sec [16, 2) [2, 64) Avg. Number of Mbits per [64, 128) Read Percentage [128+] Request (KB) Request Size Distr. Write Percent Trace % 4. Trace % 47. Trace % 6. Trace % 47.6 Trace %.4 Trace % 47. Trace % 66. Overall %.1

8 Design Space Universit of Marland ISCA 9 June 29 Focus of this stud Concurrenc Access Protocol ECC 8 Bandwidth Memor Arra Organization SSD Storage Sstem Page Mapping Wear Leveling Workload Garbage Collection OS/Driver Scheduling

9 Universit of Marland Concurrenc Banking vs. Superblocks vs. Bandwidth ISCA 9 June 29 9 Response Time (ms) Banking Superblocks 2-wa 8-wa Increasing I/O BW Response Time (ms) Banking Reads Superblocks Banking Writes Superblocks

10 Universit of Marland Request Scheduling What if we give priorit to reads? ISCA 9 June 29 1 Response Time (ms) FCFS RP 2-wa 8-wa Increasing I/O BW Response Time (ms) FCFS Reads RP Give priorit to reads Writes don t care much FCFS Writes RP

11 Universit of Marland SSD Organization Several near optimal configurations Response Time (ms) ISCA 9 June Channel 8 bit 1 MHz 8. 2 Channels 16 bit 2 MHz Bank per Channel 2 Banks per Channel 4 Banks per Channel Reads Reads Writes - MBps MBps MBps MBps MBps -

12 Universit of Marland ISCA 9 June Bottom Line Design of SSDs is a complex problem No simple solution as: Increase I/O bandwidth Increase parallelism We should model and explore the design space! Timing and Power: SLC, MLC, ECC Massive parallelism: 64, 128, 26 banks FTL algorithms: Mapping, ECC, GC, Scheduling Application specific design: DB, Web Server, etc.