SAM9G15-EK SAM9G25-EK SAM9G35-EK SAM9X25-EK SAM9X35-EK. User Guide A ATARM 27-Jul-11

Transcription

1 SAM9G-EK SAM9G-EK SAM9G-EK SAM9X-EK SAM9X-EK... User Guide A ATARM -Jul-

2 - Evaluation Kit (EK) User Guide A ATARM -Jul-

3 Section Introduction...-. Scope Applicable Documents... - Section Kit Contents...-. Deliverables Evaluation Board Specifications Electrostatic Warning...- Section Power Up...-. Power Up the Board DevStart Recovery Procedure Sample Code and Technical Support... - Section Evaluation Kit Hardware...-. Introduction Computer Module (CM) CM Board Overview Equipment List Function Blocks Configuration Connectors Schematics EK Board Description EK Board Overview Equipment List Function Blocks Configuration Connectors Schematics Optional Display Module (DM) Board Hardware DM Board Overview Equipment List Function Blocks... - Evaluation Kit (EK) User Guide A ATARM -Jul- i

4 .. Schematics... - Section Revision History...-. Revision History... - ii A ATARM -Jul- Evaluation Kit (EK) User Guide

5 Section Introduction. Scope This User Guide introduces the Evaluation Kit and describes the development and debugging capabilities running on an AT9SAM9 ARM -based Embedded MPUs as listed below: SAM9G SAM9G SAM9X SAM9G SAM9X The User Guide pertains to the following Evaluation Kit references: SAM9G-EK SAM9G-EK SAM9X-EK SAM9G-EK SAM9X-EK This User Guide gives design details on the Evaluation Kit and is made up of sections: Section includes a photo of the board, device and kit references and applicable documents. Section describes the kit contents, its main features. Section provides instructions to power up the Evaluation Kit and describes how to use it. Section describes the CPU Module (CM), the Main Board (MB) and optional Display Module (DM). Evaluation Kit (EK) User Guide - A ATARM -Jul-

6 Introduction Figure -. Board Photo (Display module is optional). Applicable Documents Table -. Applicable Documents Reference Title Comment Atmel lit 0 Atmel lit 0 Atmel lit 0 Atmel lit 0 Atmel lit 0 SAM9G datasheet SAM9G datasheet SAM9X datasheet SAM9G datasheet SAM9X datasheet These documents provide technical support for each one of the Atmel ARM-based Embedded MPU products supported by these Evaluation Kits. The datasheets can be found on in the SAM9G/SAM9X product families by means of the link below: - Evaluation Kit (EK) User Guide A ATARM -Jul-

7 Section Kit Contents. Deliverables The Evaluation Kits include: Board One EK board One of the five available CPU modules (CM) SAM9G-CM SAM9G-CM SAM9X-CM SAM9G-CM SAM9X-CM One optional DM board featured in SAM9G, SAM9G, SAM9X kits only. Power supply Universal input AC/DC power supply with US, Europe and UK plug adapters One V Lithium Battery type CR Cables One serial RS cable One micro A/B-type USB cable One RJ crossed cable A Welcome Letter Evaluation Kit (EK) User Guide - A ATARM -Jul-

8 Kit Contents Figure -. Unpacked Evaluation Kit Unpack and inspect the kit carefully. Contact your local Atmel distributor, should there be issues concerning the contents of the kit.. Evaluation Board Specifications Table -. Characteristics Clock speed Ports Board supply voltage Temperature - operating - storage Relative humidity Evaluation Kit Specifications Dimensions EK (Evaluation Kit) CM (Computer Module) DM (Display Module) Specifications 00 MHz PCK, MHz MCK Ethernet, USB, RS, DBGU, JTAG, CAN, Audio, SD Card VDC from connector -0 to +0 C -0 to + C 0 to 90% (non condensing) mm x mm. mm x mm mm x 0 mm RoHS status Compliant - Evaluation Kit (EK) User Guide A ATARM -Jul-

9 Kit Contents. Electrostatic Warning The Evaluation Kit is shipped in a protective anti-static package. The board system must not be subjected to high electrostatic potentials. A grounding strap or similar ESD protective device should be worn when handling the board in hostile ESD environments (offices with synthetic carpet, for example). Avoid touching the component pins or any other metallic element on the board. Evaluation Kit (EK) User Guide - A ATARM -Jul-

10 Section Power Up. Power Up the Board Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply. Connect the power supply DC connector to the board and plug the power supply to an AC power plug. The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the screen and enjoy the demo.. DevStart The on-board NAND Flash contains an installation guide named: SAM9x-EK DevStart. It is stored in the SAM9x-EK DevStart folder on the USB Flash disk available when the Evaluation Kit is connected to a host computer. Click the file welcome.html in this folder to launch the SAM9x-EK DevStart. DevStart guides the user through the installation processes of IAR EWARM, Keil MDK and GNU toolkits. Then, it gives step-by-step instructions on how to rebuild a single example project and how to program it into the Evaluation Kit. Optionally, if the user has a SAM-ICE interface, instructions are also given about how to debug the code. It is strongly recommended that users backup the SAM9x-EK DevStart folder on their computer before launching it. Evaluation Kit (EK) User Guide - A ATARM -Jul-

11 Power Up. Recovery Procedure The DevStart ends by giving step-by-step instructions on how to recover the Evaluation Kit to the state as it was when shipped by Atmel. Follow the instructions if contents of the NAND Flash or the SPI DataFlash have been deleted, in order to recover from this situation.. Sample Code and Technical Support After boot up, designers can run sample code or their own application, on the development kit. Users can download sample code and get technical support from the Atmel web site: Figure -. Atmel Web Site Note: Different interfaces on the EK boards share the same connections to the CPU module. Therefore the actual usage depends on the CPU module featured in the evaluation kit. - Evaluation Kit (EK) User Guide A ATARM -Jul-

12 Section Evaluation Kit Hardware. Introduction The Evaluation Kit is a fully-featured evaluation platform for the Atmel MPU. The Evaluation Kit enables users to extensively evaluate, prototype and create application-specific designs. The Evaluation Kit is a new platform architecture based on a Main Board (MB), a CPU Module (CM) equipped with one of the five processors and an optional Display Module (DM). The Evaluation Kit consists of three boards:. The CPU Module (CM) board, is a single-board computer that integrates all the core components and is mounted onto an application-specific carrier board (EK board). The CPU Module has specified pinouts based on the SODIMM00 connector. It provides the functional requirements for an embedded application. These functions include, but are not limited to, graphics, audio, mass storage, network and multiple serial and USB ports. A single SODIMM00 connector provides an interface for the carrier board to carry all the I/O signals to and from the CPU Module.. The Evaluation Kit board (EK Main Board) provides all the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a densely packed solution, which results in a more reliable product while simplifying system integration.. The optional Display Module (DM) board integrates LCD, TouchScreen and Qtouch technology. Table -, on the page that follows, lists the features provided on the Evaluation Kit: Evaluation Kit (EK) User Guide - A ATARM -Jul-

13 Table -. Evaluation Kit Features Supported modules SAM9 products Expansion Slot SO-DIMM00 Processor options SAM9 G SAM9 G SAM9 G SAM9 X SAM9 X LAN USART/UART CAN USB MII/RMII Ethernet 0/00 w/phy and three Led status RMII Ethernet 0/00 w/phy and three Led status ETH0 X X X X ETH RS four wires/rs Shared interface COM0 X X X X X RS four wires COM X X RS two wires DBGU X X X X X CAN interface Shared interface CAN0 X X CAN X X * USB.0 Host X X X X X * USB.0 Host/Device X X X X X SMD Software Modem Device X X X X X Memory Card Support ISI µsd Card Slot Onboard MMC/MMC+/SD/SDIO/CE-ATA HSMCI 0 HSMCI X X X X X X X X X X LCD + Touch Screen -bit Output Mode X X X ZigBee X X X X X SPI X X X X X TWI X X X X X DEBUG JTAG Test Access Port X X X X X X X - Evaluation Kit (EK) User Guide A ATARM -Jul-

14 . Computer Module (CM).. CM Board Overview The CM board is the CPU module at the heart of the system. It connects to the EK board through a SO- DIMM00 interface. It carries the processor and external memories. The CM board serves as a minimal CPU sub-system. All five processors:sam9g, SAM9G, SAM9X,SAM9G and SAM9X share the same CM circuitry with minor configuration settings. Note: There are three CM boards from three different manufacturers. The five processors are implemented as shown in Table - below: Table -. CM Board Implementation Manufacturer & Module kind SAM9G-CM SAM9G-CM SAM9G-CM SAM9X-CM SAM9X-CM mfg x x mfg x x mfg x x x x x The three CM boards share the same circuitry design but with different designator information and PCB layouts. The circuitry reference in this guide, for common design parts, refers to schematics from SAM9G-CM (mfg ). All the other schematics are provided in Section.. Schematics. Figure -. Board Architecture.. Equipment List The CM board is built around the integration of an ARM9-based microcontroller (BGA package) with external memory and optional Ethernet PHYsical Layer Transceiver. Evaluation Kit (EK) User Guide - A ATARM -Jul-

15 ... Devices Following is the list of the CM board components: One SAM9 Embedded MPU from the list below SAM9G SAM9G SAM9G SAM9X SAM9X MHz crystal. KHz crystal Gbit DDR memory Gits NAND Flash memory with Chip Selection control switch Mbits SPI Serial DataFlash with Chip Selection control switch Kbits EEPROM Kbyte -Wire EEPROM On-board power regulation Two user LEDs Optional PHY... Interface Connection SODIMM00 card edge interface... Configuration Items Dual ON/OFF switch for NAND Flash and SPI DataFlash Chip Select connection Figure -. CM Board Layout Commented NAND Flash DDR SDRAM Sodimm00 card edge SAM9 chip PHY - Evaluation Kit (EK) User Guide A ATARM -Jul-

16 .. Function Blocks... Processor The CM Board is equipped with an Atmel ARM-based embedded MPU, as listed below, in a -ball BGA package. The five devices share an identical footprint. All five share the same CM Board PCB with minor configuration differences. The five devices are: SAM9G SAM9G SAM9G SAM9X SAM9X As different interfaces can be defined using the same pins, it depends on the actual configuration of the CPU as to which functions are in fact available to the EK board. Refer to Section... Chip Identification for details. The processor runs at a nominal frequency of 00 MHz for the core and MHz for the system bus. The peripheral configuration possibilities and implementation requirements of the CM are dependent on the module's chipset. Two configuration resistors are implemented on board in order to select the mode of configuration.... Clock Circuitry The CM includes clock sources: Two are alternatives for the processor main clock One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip Table -. Main Components Associated with the Clock Systems Quantity Description Component assignment Crystal for Internal Clock, MHz Y Crystal for RTC Clock,. khz Y Oscillator for Ethernet Clock RMII, 0 MHz Y... Reset Circuitry The reset sources for the CM board are: Power on reset Push button reset (Push button is equipped on EK board) JTAG reset from an in-circuit emulator (JTAG interface is equipped on EK board) Evaluation Kit (EK) User Guide - A ATARM -Jul-

17 ... Power Supplies The CM Board is driven by +V input power rail from the EK board through the SODIMM00 connector. The CM Board embeds all the necessary power rails required for the micro processor. When additional voltages are required, for example VDDCORE, they are generated on board from the.v supply. The detailed power supply requirements for any given module are specified within the corresponding product documentation. The following table summarizes the power specifications. Table -. Power Rails Associated with the Systems Nominal Name Powers Component.v VDDNF the NAND Flash I/O and control, D-D and multiplexed SMC lines From SODIMM00 connector.v Partial Peripheral I/O lines From SODIMM00 connector.v VDDIOP Partial Peripheral I/O lines From SODIMM00 connector.0v VDDBU the Slow Clock oscillator, the internal khz RC, the internal MHz RC and a part of the System Controller From SODIMM00 connector.v VDDUTMII the USB device and host UTMI+ interface From SODIMM00 connector.v VDDOSC the Main Oscillator cells From SODIMM00 connector.v VDDANA the Analog to Digital Converter From SODIMM00 connector.v VDDIOM the External Memory Interface I/O lines on-board.0v VDDUTMIC DC Supply UDPHS and UHPHS UTMI+ Core on-board.v VDDPLLUTMI DC Supply UDPHS and UHPHS UTMI+ Interface From SODIMM00 connector.0v VDDPLLA the PLLA cell on-board.0v VDDCORE.0V or.v configurable the core, including the processor, the embedded memories and the peripherals on-board ADVREF ADC Reference voltage From SODIMM00 connector - Evaluation Kit (EK) User Guide A ATARM -Jul-

18 Figure -. CM Power Supply +V MN AS0EHT-adj IN LX C0.uF PWR_EN EN GND FB L.uH D C pf R 9.K % C 0uF C.uF C 00nF C 00nF C 00nF VDDCORE R 9K % PWR_EN C.uF MN AS0EHT-adj IN LX EN GND FB L.uH D C9 pf R K % C 0uF C 00nF C 00nF C 00nF VDDIOM R 9K % B VDDNF 0 OHM@00MHZ C 00nF C 00nF L 0uH/0mA VDDUTMII C 00nF R R L 0uH/0mA C9.uF C0 00nF VDDOSC C 00nF R R C 00nF C.uF C uf PWR_EN MN TPS0DCK IN OUT EN GND NR C 0nF +V C uf C 00nF L 0uH/0mA C.uF R R C 00nF VDDPLLA ADVREF C 00nF VDDBU ADVREF VDDBU C0 00nF VDDUTMIC C uf C 00nF VDDANA L VDDANA C0 00nF C 00nF VDDIOP C 00nF VDDIOP C 00nF 0uH/0mA C.uF R0 R C 00nF C 00nF Evaluation Kit (EK) User Guide - A ATARM -Jul-

19 ... Memory The Device serial processor features a DDR/SDR memory interface and an External Bus Interface (EBI) to enable interfacing to a wide range of external memories and to almost any kind of parallel peripheral. The External Bus Interface (EBI) is connected to two kinds of memory devices: One Gbyte DDR SDRAM One Gbytes (or Gbytes depending on supplier) NAND Flash - Evaluation Kit (EK) User Guide A ATARM -Jul-

20 Figure -. CM Board External Memory DDR_D0 DDR_D DDR_D DDR_D DDR_D DDR_D DDR_D DDR_D DDR_D DDR_D9 DDR_D0 DDR_D DDR_D DDR_D DDR_D DDR_D RRB RRA RRC RRD RRA RRC RRB RRD RRD RRB RRA RRB RRC RRD RRA RRC EBI_D0 EBI_D EBI_D EBI_D EBI_D EBI_D EBI_D EBI_D EBI_D EBI_D9 EBI_D0 EBI_D EBI_D EBI_D EBI_D EBI_D R R R R R R R9 R EBI_DQM0 EBI_DQM EBI_DQS0 EBI_DQS NCS0 EBI_NCS_SDCS PD PD PD0 PD R 0K R 0R R 0K R 0K NANDOE NANDWE NANDALE NANDCLE NANDCS NANDR_B 9 9 MN VDDIOM L 0uH 0mA R.K % C 0 CLE ALE RE WE CE R R C.uF R9.K % C 0 R/B R0 R R R WP C.uF EBI_RAS EBI_CAS R R R R EBI_SDWE EBI_SDCKE EBI_SDCK EBI_NSDCK DDR_NCS EBI_NCS_SDCS SWA SWITCH--.mm I/O0 I/O I/O I/O I/O I/O I/O I/O I/O_N.C I/O9_N.C 9 0 N.C N.C N.C N.C N.C 0 N.C N.C N.C N.C9 0 N.C0 N.C N.C N.C N.C DNU DNU DNU MT9FG0AAD I/O0_N.C I/O_N.C I/O_N.C 0 I/O_N.C I/O_N.C I/O_N.C VCC VCC VCC_N.C VCC_N.C 9 VSS VSS VSS_N.C VSS_N.C C0 00nF C 00nF C 00nF C 00nF C 00nF C 00nF C 00nF C 00nF C 00nF C9 00nF DDR_VREF C0 00nF VDDNF ON SAM9x_LBGA - EBI MNF D0 D D D D D D D D D9 D0 D D D D D A0/NBS0 A/NBS/DQM/NWR A A A A A A A A9 A0 A A A A A A/BA0 A/BA A/BA A9 DQM0 DQM DQS0 DQS D D A B A B C B A C D C A B A C J H H H G G F E F G G F D C E D C B E E VDDNF VDDNF PD[..] {,} PD PD PD PD9 PD0 PD PD PD PD0 (NANDOE) R0 0R PD (NANDWE) R 0R PD (NANDALE) R 0R PD (NANDCLE) R 0R PD (NANDCS) R 0R PD (NANDR/B) R 0R EBI_D0 EBI_D EBI_D EBI_D EBI_D EBI_D EBI_D EBI_D EBI_D EBI_D9 EBI_D0 EBI_D EBI_D EBI_D EBI_D EBI_D EBI_A EBI_A EBI_A EBI_A EBI_A EBI_A EBI_A EBI_A9 EBI_A0 EBI_A EBI_A EBI_A EBI_A EBI_A EBI_A EBI_A PD0 PD PD PD PD PD PD PD PD PD9 PD0 PD PD PD PD PD PD PD PD PD9 PD0 PD DDR_SDWE DDR_SDCKE R R R R (NANDOE) (NANDWE) (NANDALE) (NANDCLE) (NANDCS) DDR_DQM0 DDR_DQM DDR_DQS0 DDR_DQS DDR_RAS DDR_CAS DDR_SDCK DDR_NSDCK R R PD NAND_FSH_D0 NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND_FSH_D MNE SAM9x_LBGA - PIOD R PD0/NANDOE P PD/NANDWE R PD/A/NANDALE R P PD/A/NANDCLE P PD/NCS P PD/NWAIT N PD/D PD/D PD/D PD9/D9 PD0/D0 PD/D PD/D PD/D PD/D PD/D/A0 PD/D/A PD/D/A PD/D/A PD9/D9/NCS PD0/D0/NCS PD/D/NCS R M N N N K M L M L L K J K J RRA RRB RRC RRD RRA RRB RRC RRD A0 B0 A A9 RAS B CAS C0 A SDWE B SDCKE C SDA0 D SDCK #SDCK C NCS0 NCS/SDCS NWR0/NWRE NWR/NBS NWR/NBS/DQM B9 B C9 C A NRD D9 EBI_DQM0 EBI_DQM EBI_DQS0 EBI_DQS EBI_RAS EBI_CAS EBI_SDWE EBI_SDCKE EBI_SDA0 EBI_SDCK EBI_NSDCK EBI_A EBI_A EBI_A EBI_A EBI_A EBI_A EBI_A EBI_A9 EBI_A0 EBI_A EBI_SDA0 EBI_A EBI_A EBI_A EBI_A EBI_A DDR_SDCKE DDR_SDCK DDR_NSDCK DDR_NCS DDR_CAS DDR_RAS DDR_SDWE DDR_DQS DDR_DQS0 DDR_DQM DDR_DQM0 EBI_A PD R0 0R R 0R R 0R R 0R CLE ALE RE WE CE RB WP R9 DNP M M M N N N N P P P M P R L L L K9 MN A0 A A A A A A A A A9 A0 A A BA0 BA BA ODT DDR SDRAM MTHMHR DQ0 DQ DQ DQ DQ DQ DQ DQ DQ DQ9 DQ0 DQ DQ DQ DQ DQ G G H H H H9 F F9 C C D D D D9 B B9 VDD A VDD E VDD J9 K CKE J K CK CK VDD M9 VDD R J VDDL VDDQ A9 L CS VDDQ C VDDQ C VDDQ C L VDDQ C9 K CAS VDDQ E9 G RAS VDDQ G G K VDDQ G G WE VDDQ G G9 VDDQ G9 B A UDQS UDQS J VREF VSS A F E LDQS LDQS VSS E VSS J VSS N VSS P9 B F UDM LDM VSSQ A VSSQ B VSSQ B VSSQ D A E R R R RFU RFU RFU RFU RFU VSSQ D VSSQ E F VSSQ F F VSSQ F H VSSQ H H VSSQ H J VSSDL DDR_D0 DDR_D DDR_D DDR_D DDR_D DDR_D DDR_D DDR_D DDR_D DDR_D9 DDR_D0 DDR_D DDR_D DDR_D DDR_D DDR_D VDDIOM C 00nF C 00nF C 00nF C 00nF C 00nF C9 00nF DDR SDRAM NAND_FSH_D0 NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND_FSH_D NAND FLASH C 00nF C 00nF Evaluation Kit (EK) User Guide -9 A ATARM -Jul-

21 ... Serial Peripheral Interface (SPI) Controller The serial processor provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to interface with the on-board serial DataFlash. Figure -. SPI PA SWB SWITCH--.mm ON PA PA PA (SPI0_MOSI) R (SPI0_MIS0) R (SPI0_SPCK) R9 (SPI0_NPCS0) 0R 0R 0R R 0K MN ATDF SI SO SCK CS VCC WP HOLD GND C9 00nF... Two Wire Interface (TWI) The serial processor has a full speed (00 khz) master/slave TWI Serial Controller. The controller is mostly compatible with industry standard IC and SMBus Interfaces. This port is used to interface with the on-board Serial EEPROM, ISI, QTouch device and audio codec interface. Figure -. TWI PA PA0 (TWCKO) (TWDO) R.K C0 00nF R.K MN ATCBN-SH-B SCL A0 SDA A A VCC GND WP R 0K R DNP... -Wire EEPROM The Evaluation Kit uses a -Wire device as firmware label to store the information such as chip type, manufacturer s name, production date etc. Figure -. -Wire Device VDDANA PB R 0R R.K MN9 DSP+ IO GND NC NC NC NC -0 Evaluation Kit (EK) User Guide A ATARM -Jul-

22 ...9 Optional PHY Some of the device modules provide a location for a 0/00 Ethernet MAC/PHY interface. For more information about the Ethernet controller device, refer to the Davicom DM9 controller manufacturer's datasheet. Evaluation Kit (EK) User Guide - A ATARM -Jul-

23 Figure -. Ethernet PB[0..] DNP to remain single PHY connection on EK board PB E0_TXCK R R PB0 E0_TX PB9 E0_TX0 PB E0_TXEN RRB RRC RRD PB PB0 E0_RX E0_RX0 RRC RRD PB E0_RXDV RRB PB E0_RXER RRC PB PB PB E0_MDC E0_MDIO E0_INTR RRA RRB RRA NRST VDDANA RR 0KX RR 0KX R9 DNP R9.K R9 0K R9 0K 0MHz VSS OUT Y OE VDD R0 0K GND_ETH R00 0R + C 0uF VDDANA R9 DNP RXD/PHYAD RXD/PHYAD 9 RXD/PHYAD TP SMD RXD0/PHYAD0 RX+ RX_CLK/0BTSER RX_DV/TESTMODE RX- TX_ER/TXD RX_ER/RXD/RPTR COL/RMII AVDDR CRS/PHYAD VDDANA R.K AVDDR MDC DM9AEP MDIO 9 MDINTR AVDDT 9 DISMDIX AGND AGND VDDANA AGND C9 00nF DVDD BGRESG C0 00nF 0 DVDD C 00nF DVDD BGRES DGND LEDMODE DGND LED0/OP0 DGND LED/OP R99 0R 0 LED/OP PWRDWN CABLESTS/LINKSTS 0 RESET N.C TX- MN0 REF_CLK/XT TXD 9 TXD 0 TXD TXD0 TX_EN TX_CLK/ISOLATE TX+ R R XT C 00nF VDDANA C 00nF C 00nF AVDDT C 00nF R9 0R R9.K 0K 0KX R9 RR9 GND_ETH VDDANA + C 0uF + C 0uF BLMBDTN B AVDDT R 9.9R % TP SMD R 9.9R % C 00nF R 9.9R % R 9.9R % C 00nF GND_ETH GND_ETH ETH0_TX+ ETH0_RX- ETH0_TX- ETH0_RX+ LED0 LED LED - Evaluation Kit (EK) User Guide A ATARM -Jul-

24 Evaluation Kit (EK) User Guide - A ATARM -Jul-...0 SODIMM00 Interface The CM board uses SODIMM00 card edge connector to interface with the EK board. Figure -9. SODIMM00 Interface on CM Board HHSDMC PB PB PB PB PD0 PD PD PD VDDIOP PWR_EN +V PA PA0 PA PA PC PC PC PC0 PC C uf NANDCS VDDNF C 0uF PD PC PC PC PC0 PC NRST PD R0 0R ETH0_TX+ PC PC PC PC PC PC0 PD0 R0 DNP ETH0_TX- PA NANDOE PA PA9 PA PA PA VDDNF J PIO 00-pin SODIMM VCC_V VCC_V VCC_V VCC_V GND VBAT USBC_DP JTAGSEL USBC_DM 9 WKUP 0 GND SHDN USBB_DM BMS USBB_DP nrst GND ntrst DIBP 9 TDI 0 DIBN TCK GND TMS USBA_DM TDO USBA_DP RTCK GND 9 PWR_EN 0 RFU RFU RFU RFU RFU RFU RFU RFU RFU9 9 RFU0 0 GND GND RFU RFU RFU RFU RFU RFU RFU 9 RFU 0 GND GND RFU9 RFU0 RFU RFU RFU RFU RFU 9 RFU 0 VDDNF VDDNF PD0 PD PD PD PD PD PD 9 PD 0 PD PD9 NC GND PD0 PD PD PD PD 9 PD 0 PD PD PD PD9 PD0 PD PA0 9 PA 90 PA 9 PA 9 PA 9 GND 9 PA 9 PA 9 PA 9 PA 9 GND 99 PA 00 PA 0 PA 0 PA 0 PA 0 PA 0 PA0 0 GND 0 PA 0 PA 09 PA 0 PA PA9 PA0 GND PA PA PA0 PA9 GND 9 PA 0 PA PA PA PA PA9 GND VDDIOP VDDIOP PC0 9 PC 0 PC PC PC PC GND PC PC PC PC9 9 PC0 0 PC GND PC PC PC PC GND PC PC 9 PC 0 PC9 PC0 PC GND PC PC PC PC PC 9 PC 0 GND PC PC9 PC0 PC SELCONFIG0 VDDANA VDDANA PB0 9 PB 0 PB PB PB PB PB PB PB GNDANA PB9 9 PB0 0 PB PB PB PB PB PB PB GNDANA PB 9 ADVREF 90 GND 9 LED0 9 ETH0_TX+ 9 LED 9 ETH0_TX- 9 LED 9 ETH0_RX+ 9 AVDDT 9 ETH0_RX- 99 GND_ETH 00 ETH0_RX+ PA PA PA PA0 PA PA PA9 PA PA C.uF +V ADVREF PA PA0 PA PA PA0 JTAGSEL VDDANA NANDALE PA PA PA VDDIOP PA PA PA9 ETH0_RX- WKUP PA PA HHSDMB HHSDPB PC PC PC0 NANDR_B BMS PC9 PC PC PC PC NANDWE PD PD PD9 PD PD PD LED0 PC PC9 PC PC PC NTRST DIBN DIBP PD9 PD PD PC TDI NANDCLE HHSDPA HHSDMA R0 only if G, G, X LED PC9 PC TCK GND_ETH AVDDT TMS LED R0 only if G, X SHDN PB0 PB PB PB PB PB9 C uf PB PB PB PB PB HHSDPC C.uF TDO C.uF VDDANA +V VDDBU RTCK PB PB PB0 PB

25 .. Configuration... Chip Identification The CM board may be equipped with any of the five processors, all sharing an identical BGA footprint. There are two resistors on the CM board for the purpose of identifying which of the five is the one actually mounted. The tables below show in detail how the CM board, relative to different processors, determines the dedicated SELCONFIG logic. Table -. Resistor Identification Resistor SAM9G SAM9G SAM9G SAM9X SAM9X R9 Populated Not Populated R0 Not Populated Populated R Populated Populated R Not Populated Not Populated R0 Populated Not Populated Populated Not Populated Populated R0 Not Populated Populated Not Populated Populated Not Populated Table -. Module Configuration Identification CM Setting EK Setting DM Setting SAM9G module SAM9G module SAM9X module SAM9G module SAM9X module R0 Populated Populated Populated Not Populated Not Populated R0 Not Populated Not Populated Not Populated Populated Populated SELCONFIG (SODIMM00 pin ) High High High Low Low USART Not Selected Not Selected Not Selected Selected Selected ETH Not Selected Not Selected Not Selected Not Selected Selected LCD Selected Selected Selected Not Selected Not Selected - Evaluation Kit (EK) User Guide A ATARM -Jul-

26 ... Boot Configuration In order to use SAM-BA boot, the NAND Flash and SPI DataFlash must be deselected. SW is dedicated to this purpose. Table -. Boot Configuration Designation Default Setting Feature SW (, ) ON Set to OFF disables the NAND flash SW (, ) ON Set to OFF disables the SPI DataFlash.. Connectors Figure -0. CM Board Dimensions Evaluation Kit (EK) User Guide - A ATARM -Jul-

27 Evaluation Kit Hardware.. Schematics Figure -. CM Board Schematics of +V MN VDDIOM +V MN VDDCORE MNA AS0EHT-adj L AS0EHT-adj L SAM9X_LBGA - POWER TP.uH D IN LX H IN LX GNDCORE H SMD.uH D K VDDCORE C GNDCORE J C C K9 VDDCORE D C C9 R C C R C C 00nF GNDCORE K0 C0 00nF 00nF VDDCORE K % 9.K % D.uF pf 0uF.uF pf 0uF.uF EN FB +V EN FB VDDIOM R R D0 9K % 9K % D VDDIOM R C GNDIOM H9 C F VDDIOM DNP C H0 00nF 00nF 00nF VDDIOM GNDIOM GNDIOM J9 TP SMD {} {} {} PWR_EN HHSDMA HHSDPA PWR_EN PWR_EN C 0pF C C B VDDANA L TST C T VDDANA GNDUTMI 0uH/0mA R0 C C A C 0pF C 00nF 00nF XIN 00nF R +V MN +V TPS0DCK +V IN OUT EN NR C uf VDDNF C 00nF C 00nF VDDIOP C 00nF {} BMS R 00K VDDBU C9 0pF +V L 0uH/0mA +V C0 00nF R R R R R C DNP 00K 00K 00K NTRST TP.K 0pF C R SMD 00nF D R C TDI TP JTAGSEL JTAGSEL {} 00nF SMD T NTRST C NTRST NTRST {} T9 TDI.uF TMS TP TDI TDI {} TMS TMS U SMD TMS {} TCK TCK U0 TCK {} RTCK RTCK {} TCK TP RTCK R0 TDO B TDO {} SMD TDO T0 B ADVREF TP A RTCK TP R 00K SMD ADVREF SMD R9 9R P P0 NRST C NRST {,} R0 9R R HFSDMB NRST 00nF TDO HFSDPB GNDBU B TP9 SMD P {} HHSDMB R HHSDMB NRST TP0 {} HHSDPB HHSDPB VDDBU SMD TP SMD VDDBU WKUP TP L B SMD R 00K +V 0uH/0mA VDDBU C C SHDN TP uf 00nF SMD WKUP C WKUP A R WKUP {} 00nF GNDOSC U R R M R {} HHSDMC R R L HFSDMC U {} HHSDPC HFSDPC C9 VDDUTMII.uF C0 00nF R {} DIBN DIBN L P +V {} DIBP DIBP 0uH/0mA SHDN SHDN D T SHDN {} VDDOSC C R C 00nF 00nF A A R C +V.uF TP TP TP SMD SMD SMD +V VDDIOP TP TP TP9 Title: SMD SMD SMD MBC-SAM9X VDDANA VDDNF TP0 TP TP Size: Document Number: Rev: SMD SMD SMD A AT9SAM9G-I&POWER A Draw By: Zhu Xueliang Thursday, November 0, 00 Date: Sheet: of GND T T U U MNG SAM9x_LBGA - INTERFACE HFSDMA HFSDPA HHSDMA HHSDPA XIN T XOUT U C 0nF C0 00nF P9 U BMS VBG XOUT A GND R 9R R 9R C9 0pF B 0 OHM@00MHZ C 00nF J K P H VDDNF VDDNF VDDIOP GNDIOM J0 GNDIOP M GNDIOP P GNDANA D Y. khz C.uF T R VDDUTMIC VDDPLLA GND Y MHz C uf - Evaluation Kit (EK) User Guide A ATARM -Jul-

28 9 Evaluation Kit Hardware Figure -. CM Board Schematics of MN EBI_A M G DDR_D0 MNF EBI_A M A0 DDR SDRAM DQ0 G DDR_D SAM9x_LBGA - EBI EBI_A M A DQ MTHMHR H DDR_D D EBI_D0 EBI_A N A DQ H DDR_D D0 D EBI_D EBI_A N A DQ H DDR_D D A EBI_D EBI_A N A DQ H9 DDR_D D B EBI_D EBI_A N A DQ F DDR_D D A EBI_D EBI_D0 RRB DDR_D0 EBI_A9 P A DQ F9 DDR_D D B EBI_D EBI_D RRA DDR_D EBI_A0 P A DQ C DDR_D D C EBI_D EBI_D RRC DDR_D EBI_A P A DQ C DDR_D9 D D B EBI_D EBI_D RRD DDR_D EBI_SDA0 M A9 DQ9 D DDR_D0 D D A EBI_D EBI_D RRA DDR_D EBI_A P A0 DQ0 D DDR_D D C EBI_D9 EBI_D RRC DDR_D EBI_A R A DQ D DDR_D D9 D EBI_D0 EBI_D RRB DDR_D A DQ D9 DDR_D D0 C EBI_D EBI_D RRD DDR_D EBI_A L DQ B DDR_D D A EBI_D EBI_D RRD DDR_D EBI_A L BA0 DQ B9 DDR_D D B EBI_D EBI_D9 RRB DDR_D9 EBI_A L BA DQ D A EBI_D EBI_D0 RRA DDR_D0 BA VDDIOM D C EBI_D EBI_D RRB DDR_D K9 D EBI_D DDR_D ODT VDD A J EBI_D DDR_D VDD E C 00nF RRC A0/NBS0 H EBI_D RRA DDR_D VDD J9 C 00nF RRD C 00nF A/NBS/DQM/NWR H EBI_A EBI_D RRC DDR_D DDR_SDCKE VDD M9 K A H EBI_A CKE VDD R C 00nF C 00nF A G EBI_A DDR_SDCK J J A G EBI_A DDR_NSDCK CK VDDL C9 00nF K A F EBI_A CK A E EBI_A VDDQ A9 A F EBI_A DDR_NCS L VDDQ C C0 00nF DDR SDRAM A G EBI_A9 CS VDDQ C C 00nF A9 C 00nF G EBI_A0 VDDQ C C 00nF A0 F EBI_A DDR_CAS L VDDQ C9 A D DDR_RAS VDDQ E9 C 00nF K CAS A C EBI_A RAS VDDQ G C 00nF A E EBI_A DDR_SDWE K VDDQ G C 00nF A C 00nF D EBI_A EBI_DQM0 DDR_DQM0 WE VDDQ G C 00nF R R VDDIOM A C EBI_A EBI_DQM DDR_DQM VDDQ G9 C9 00nF R R A/BA0 B EBI_A EBI_DQS0 R R DDR_DQS0 DDR_DQS B J DDR_VREF A/BA E EBI_A EBI_DQS R9 R DDR_DQS A UDQS VREF C A/BA E UDQS C A9 EBI_RAS R0 R DDR_RAS VSS A L A0 EBI_DQM0 EBI_CAS R R DDR_CAS DDR_DQS0 VSS E C0 C F 0uH DQM0 B0 EBI_DQM VSS J 00nF.uF E LDQS 0mA DQM A EBI_DQS0 EBI_SDWE R R DDR_SDWE LDQS VSS N DQS0 A9 EBI_DQS EBI_SDCKE R R DDR_SDCKE VSS P9 DQS DDR_DQM B EBI_RAS EBI_SDCK R R DDR_SDCK DDR_DQM0 RAS B F UDM VSSQ A EBI_CAS EBI_NSDCK DDR_NSDCK CAS C0 R R LDM VSSQ B VSSQ B R.K % C 0 R R DDR_NCS R R EBI_NCS_SDCS TP SMD DDR_VREF RFU RFU RFU RFU RFU A E R R R EBI_SDWE EBI_SDCKE EBI_SDA0 EBI_SDCK EBI_NSDCK EBI_A SDWE A SDCKE B C SDA0 SDCK D #SDCK C R9.K % C 0 C.uF VSSQ D VSSQ D VSSQ E VSSQ F VSSQ F VSSQ H VSSQ H J VSSDL NCS0 EBI_NCS_SDCS B9 NCS0 NCS/SDCS B C9 NWR0/NWRE C NWR/NBS A NWR/NBS/DQM NCS0 TP NRD D9 SMD MN B B PD R0 0R CLE 9 NAND_FSH_D0 PD R 0R ALE CLE I/O0 0 NAND_FSH_D SWA PD0 R 0R RE ALE I/O NAND_FSH_D SWITCH--.mm PD R 0R WE RE I/O NAND_FSH_D PD CE WE I/O NAND_FSH_D VDDNF R 0K CE I/O NAND_FSH_D PD R 0R RB I/O NAND_FSH_D MNE R 0K R/B I/O NAND_FSH_D SAM9x_LBGA - PIOD VDDNF R 0K WP 9 I/O PD0 (NANDOE) PD0/NANDOE P WP I/O_N.C PD (NANDWE) PD/NANDWE R I/O9_N.C PD (NANDALE) PD/A/NANDALE R I/O0_N.C PD (NANDCLE) PD/A/NANDCLE P N.C I/O_N.C PD[..] {,} P PD (NANDCS) R9 N.C I/O_N.C 0 PD/NCS DNP P PD N.C I/O_N.C PD/NWAIT N PD N.C I/O_N.C NAND FLASH PD/D R PD N.C I/O_N.C PD/D M PD 0 N.C VDDNF PD/D N PD9 PD RRA NAND_FSH_D0 N.C PD9/D9 N PD0 PD NAND_FSH_D VCC RRB N.C PD0/D0 N PD PD NAND_FSH_D VCC RRC N.C9 PD/D K PD PD9 NAND_FSH_D 0 VCC_N.C RRD N.C0 PD/D M PD PD0 NAND_FSH_D N.C VCC_N.C 9 RRA C C PD/D L PD PD RRB NAND_FSH_D N.C 00nF 00nF PD/D M PD PD RRC NAND_FSH_D N.C PD/D/A0 L PD PD NAND_FSH_D N.C VSS RRD PD/D/A L PD DNU VSS PD/D/A K PD DNU VSS_N.C PD/D/A J PD9 DNU VSS_N.C A PD9/D9/NCS A K PD0 MT9FG0AAD PD0/D0/NCS J PD PD0 (NANDOE) R0 0R PD/D/NCS NANDOE {} PD (NANDWE) R 0R NANDWE {} PD (NANDALE) R 0R NANDALE {} PD (NANDCLE) R 0R NANDCLE {} PD (NANDCS) R 0R NANDCS {} PD (NANDR/B) R 0R NANDR_B {} Title: MBC-SAM9X ON Size: Document Number: Rev: A AT9SAM9G-II&DDR&NAND FLASH A Draw By: Zhu Xueliang Date: Thursday, November 0, 00 Sheet: of Evaluation Kit (EK) User Guide - A ATARM -Jul-

29 9 Evaluation Kit Hardware Figure -. CM Board Schematics of MN EBI_A M G DDR_D0 MNF EBI_A M A0 DDR SDRAM DQ0 G DDR_D SAM9x_LBGA - EBI EBI_A M A DQ MTHMHR H DDR_D D EBI_D0 EBI_A N A DQ H DDR_D D0 D EBI_D EBI_A N A DQ H DDR_D D A EBI_D EBI_A N A DQ H9 DDR_D D B EBI_D EBI_A N A DQ F DDR_D D A EBI_D EBI_D0 RRB DDR_D0 EBI_A9 P A DQ F9 DDR_D D B EBI_D EBI_D RRA DDR_D EBI_A0 P A DQ C DDR_D D C EBI_D EBI_D RRC DDR_D EBI_A P A DQ C DDR_D9 D D B EBI_D EBI_D RRD DDR_D EBI_SDA0 M A9 DQ9 D DDR_D0 D D A EBI_D EBI_D RRA DDR_D EBI_A P A0 DQ0 D DDR_D D C EBI_D9 EBI_D RRC DDR_D EBI_A R A DQ D DDR_D D9 D EBI_D0 EBI_D RRB DDR_D A DQ D9 DDR_D D0 C EBI_D EBI_D RRD DDR_D EBI_A L DQ B DDR_D D A EBI_D EBI_D RRD DDR_D EBI_A L BA0 DQ B9 DDR_D D B EBI_D EBI_D9 RRB DDR_D9 EBI_A L BA DQ D A EBI_D EBI_D0 RRA DDR_D0 BA VDDIOM D C EBI_D EBI_D RRB DDR_D K9 D EBI_D DDR_D ODT VDD A J EBI_D DDR_D VDD E C 00nF RRC A0/NBS0 H EBI_D RRA DDR_D VDD J9 C 00nF RRD C 00nF A/NBS/DQM/NWR H EBI_A EBI_D RRC DDR_D DDR_SDCKE VDD M9 K A H EBI_A CKE VDD R C 00nF C 00nF A G EBI_A DDR_SDCK J J A G EBI_A DDR_NSDCK CK VDDL C9 00nF K A F EBI_A CK A E EBI_A VDDQ A9 A F EBI_A DDR_NCS L VDDQ C C0 00nF DDR SDRAM A G EBI_A9 CS VDDQ C C 00nF A9 C 00nF G EBI_A0 VDDQ C C 00nF A0 F EBI_A DDR_CAS L VDDQ C9 A D DDR_RAS VDDQ E9 C 00nF K CAS A C EBI_A RAS VDDQ G C 00nF A E EBI_A DDR_SDWE K VDDQ G C 00nF A C 00nF D EBI_A EBI_DQM0 DDR_DQM0 WE VDDQ G C 00nF R R VDDIOM A C EBI_A EBI_DQM DDR_DQM VDDQ G9 C9 00nF R R A/BA0 B EBI_A EBI_DQS0 R R DDR_DQS0 DDR_DQS B J DDR_VREF A/BA E EBI_A EBI_DQS R9 R DDR_DQS A UDQS VREF C A/BA E UDQS C A9 EBI_RAS R0 R DDR_RAS VSS A L A0 EBI_DQM0 EBI_CAS R R DDR_CAS DDR_DQS0 VSS E C0 C F 0uH DQM0 B0 EBI_DQM VSS J 00nF.uF E LDQS 0mA DQM A EBI_DQS0 EBI_SDWE R R DDR_SDWE LDQS VSS N DQS0 A9 EBI_DQS EBI_SDCKE R R DDR_SDCKE VSS P9 DQS DDR_DQM B EBI_RAS EBI_SDCK R R DDR_SDCK DDR_DQM0 RAS B F UDM VSSQ A EBI_CAS EBI_NSDCK DDR_NSDCK CAS C0 R R LDM VSSQ B VSSQ B R.K % C 0 R R DDR_NCS R R EBI_NCS_SDCS TP SMD DDR_VREF RFU RFU RFU RFU RFU A E R R R EBI_SDWE EBI_SDCKE EBI_SDA0 EBI_SDCK EBI_NSDCK EBI_A SDWE A SDCKE B C SDA0 SDCK D #SDCK C R9.K % C 0 C.uF VSSQ D VSSQ D VSSQ E VSSQ F VSSQ F VSSQ H VSSQ H J VSSDL NCS0 EBI_NCS_SDCS B9 NCS0 NCS/SDCS B C9 NWR0/NWRE C NWR/NBS A NWR/NBS/DQM NCS0 TP NRD D9 SMD MN B B PD R0 0R CLE 9 NAND_FSH_D0 PD R 0R ALE CLE I/O0 0 NAND_FSH_D SWA PD0 R 0R RE ALE I/O NAND_FSH_D SWITCH--.mm PD R 0R WE RE I/O NAND_FSH_D PD CE WE I/O NAND_FSH_D VDDNF R 0K CE I/O NAND_FSH_D PD R 0R RB I/O NAND_FSH_D MNE R 0K R/B I/O NAND_FSH_D SAM9x_LBGA - PIOD VDDNF R 0K WP 9 I/O PD0 (NANDOE) PD0/NANDOE P WP I/O_N.C PD (NANDWE) PD/NANDWE R I/O9_N.C PD (NANDALE) PD/A/NANDALE R I/O0_N.C PD (NANDCLE) PD/A/NANDCLE P N.C I/O_N.C PD[..] {,} P PD (NANDCS) R9 N.C I/O_N.C 0 PD/NCS DNP P PD N.C I/O_N.C PD/NWAIT N PD N.C I/O_N.C NAND FLASH PD/D R PD N.C I/O_N.C PD/D M PD 0 N.C VDDNF PD/D N PD9 PD RRA NAND_FSH_D0 N.C PD9/D9 N PD0 PD NAND_FSH_D VCC RRB N.C PD0/D0 N PD PD NAND_FSH_D VCC RRC N.C9 PD/D K PD PD9 NAND_FSH_D 0 VCC_N.C RRD N.C0 PD/D M PD PD0 NAND_FSH_D N.C VCC_N.C 9 RRA C C PD/D L PD PD RRB NAND_FSH_D N.C 00nF 00nF PD/D M PD PD RRC NAND_FSH_D N.C PD/D/A0 L PD PD NAND_FSH_D N.C VSS RRD PD/D/A L PD DNU VSS PD/D/A K PD DNU VSS_N.C PD/D/A J PD9 DNU VSS_N.C A PD9/D9/NCS A K PD0 MT9FG0AAD PD0/D0/NCS J PD PD0 (NANDOE) R0 0R PD/D/NCS NANDOE {} PD (NANDWE) R 0R NANDWE {} PD (NANDALE) R 0R NANDALE {} PD (NANDCLE) R 0R NANDCLE {} PD (NANDCS) R 0R NANDCS {} PD (NANDR/B) R 0R NANDR_B {} Title: MBC-SAM9X ON Size: Document Number: Rev: A AT9SAM9G-II&DDR&NAND FLASH A Draw By: Zhu Xueliang Date: Thursday, November 0, 00 Sheet: of - Evaluation Kit (EK) User Guide A ATARM -Jul-

30 Evaluation Kit Hardware Figure -. CM Board Schematics of D D VDDANA R0 0K Y OE VDD 0MHz VSS OUT C 00nF C 00nF GND_ETH RX- {,} PB[0..] MN0 R R PB E0_TXCK R R R R REF_CLK/XT XT 9.9R % 9.9R % TXD PB0 E0_TX RRB 9 TXD ETH0_TX+ {} PB9 E0_TX0 RRC 0 TXD TX+ PB E0_TXEN RRD TXD0 TP TX_EN SMD TX_CLK/ISOLATE ETH0_TX- {} C TX- C RXD/PHYAD PB E0_RX RRC RXD/PHYAD PB0 E0_RX0 RRD 9 RXD/PHYAD RXD0/PHYAD0 RX+ ETH0_RX+ {} PB PB PB PB PB E0_RXDV E0_RXER E0_MDC E0_MDIO E0_INTR Install as need to alter PHYaddress, must override internal pullup on SAM9x RRB RRC RRA RRB RRA VDDANA VDDANA C0 00nF 0 R9 RR9 DVDD R9.K C 00nF 0K 0KX DVDD RR RR BGRES B B 0KX 0KX DGND LEDMODE LED0 {} DGND LED0/OP0 DGND LED/OP LED {} VDDANA LED {} R99 0R 0 LED/OP PWRDWN CABLESTS/LINKSTS {,} NRST R.K C9 00nF 9 RX_CLK/0BTSER RX_DV/TESTMODE TX_ER/TXD RX_ER/RXD/RPTR COL/RMII CRS/PHYAD MDC MDIO MDINTR DM9AEP AVDDR AVDDR C 00nF AVDDT C 00nF R9 0R + C 0uF B BLMBDTN VDDANA AVDDT + C 0uF GND_ETH TP SMD R 9.9R % GND_ETH R 9.9R % C 00nF ETH0_RX- {} R9 DNP R9.K R9 0K 0 DISMDIX DVDD RESET AVDDT AGND AGND AGND BGRESG N.C C 00nF VDDANA + C 0uF R00 0R GND_ETH ETHERNET A A Title: MBC-SAM9X Size: Document Number: Rev: A ETHERNET A Draw By: Zhu Xueliang Thursday, November 0, 00 Date: Sheet: of 9 R9 0K R9 DNP Evaluation Kit (EK) User Guide -9 A ATARM -Jul-

31 Evaluation Kit Hardware Figure -. CM Board Schematics of +V VDDBU C +V C 0uF J uf VCC_V VCC_V VCC_V VCC_V GND VBAT {} PA[0..] {} HHSDPC USBC_DP JTAGSEL JTAGSEL {} {} HHSDMC PA0 USBC_DM WKUP 0 WKUP {} PA GND SHDN SHDN {} {} HHSDMB PA USBB_DM BMS BMS {} {} HHSDPB NRST {,} D PA USBB_DP nrst NTRST {} D PA 9 GND ntrst 0 {} DIBP TDI {} PA DIBP TDI {} DIBN PA DIBN TCK TCK {} PA GND TMS TMS {} {} HHSDMA PA USBA_DM TDO TDO {} {} HHSDPA PA9 USBA_DP RTCK RTCK {} 9 PA0 GND PWR_EN 0 PWR_EN {} PA RFU RFU PA RFU RFU PA RFU RFU PA 9 RFU RFU 0 PA RFU9 RFU0 VDDNF PA PA GND GND PA RFU RFU PA9 RFU RFU PA0 VDDNF 9 RFU RFU 0 C PA RFU RFU.uF PA GND GND PA RFU9 RFU0 PA RFU RFU PA 9 RFU RFU 0 PA RFU RFU PA VDDNF VDDNF {} NANDOE NANDWE {} PA PD0 PD {} NANDALE NANDCLE {} PA9 PD PD PD {} NANDCS PA0 9 PD PD 0 PD {} NANDR_B PA PD PD PD PD9 C PD PD9 C PD0 NC GND PD PD PD0 PD PD PD 9 PD PD 0 PD {,} PB[0..] PD PD PD PD PB0 PD PD PD PD9 PB PD0 PD PD9 PD PB PD0 PD PB PA PA PB PA 9 PA0 PA 9 PA PB PA 9 PA PA C PB PA PA GND PA.uF PD[..] {,} PB PA 9 PA PA 9 PA PB 99 PA PA 00 PA PB9 PA 0 GND PA 0 PA PB0 PA 0 PA PA 0 PA PD PB PA 0 PA PA 0 PA0 PD PB 0 PA PA0 0 PA PD PB PA 09 GND PA 0 PA PD9 PB PA PA PA PA9 PD0 PB PA0 PA PA9 PD PB PA PA0 GND PA PD PB PA0 PA PA PA9 PD PB 9 PA0 PA9 0 PA PD PA GND PA PA PD PA PA PA PA PD VDDIOP PA9 PA PA VDDIOP PD PA9 GND PD {} PC[0..] PC0 9 VDDIOP VDDIOP 0 PC PD9 B B PC0 PC PC0 PC PC PD0 PC PC PC PC PC C PD PC PC PC PC.uF PC PC GND PC PC PC PC9 9 PC PC 0 PC0 PC PC PC9 PC0 PC PC PC GND PC PC PC PC PC PC PC PC PC PC PC9 PC 9 GND PC 0 PC +V PC0 PC9 PC PC PC0 PC PC PC9 PC0 PC PC PC GND PC PC PC PC PC PC R0 PC PC 9 PC PC 0 PC DNP PC PC PC PC PC PC9 GND PC PC0 PC PC PC9 PC0 PC VDDANA PC SELCONFIG0 VDDANA PC9 PB0 VDDANA VDDANA 9 0 PB PC0 PB PB0 PB PB R0 PC PB PB PB PB ADVREF 0R PC PB PB PB PB PC PB PB PB PC PB9 PB GNDANA 9 0 PB0 PC PB PB9 PB0 PB C PC PB PB PB PB uf PC PB PB PB PB PC PB PB PB A A PC9 PB PB GNDANA 9 90 PC0 9 PB ADVREF 9 LED0 {} PC 9 GND LED0 9 {} ETH0_TX+ LED {} 9 ETH0_TX+ LED 9 {} ETH0_TX- LED {} 9 ETH0_TX- LED 9 {} ETH0_RX+ ETH0_RX+ AVDDT 99 AVDDT {} ETH0_RX- ETH0_RX- GND_ETH 00 PIO 00-pin SODIMM Title: MBC-SAM9X GND_ETH Size: Document Number: Rev: A AT9SAM9G-II A Draw By: Zhu Xueliang Thursday, November 0, 00 Date: Sheet: of 9-0 Evaluation Kit (EK) User Guide A ATARM -Jul-

32 . EK Board Description.. EK Board Overview The EK board serves as the main board that carries the CPU module. It features all necessary peripherals and interfaces for processor evaluation. Figure -. Commented EK Board Layout Evaluation Kit (EK) User Guide - A ATARM -Jul-

33 .. Equipment List Based on the processor installed on the CM board, the EK board is equipped with the following interfaces or peripherals:... Devices List of the EK board peripherals: Two EMAC PHY One Audio codec Two high speed MCI Card interfaces Two CAN transceivers Three RS ports with level translator features: DBGU, USART0 and USART One Smart DAA port Two USB host ports One USB host/device port On-board power regulation LCD/ISI extension interface ZigBee interface One-wire device... Board Interface Connection Main power supply (J) One SODIMM00 socket (CON) USB A Host/Device, support USB host/device using a type micro AB connector (J0) USB B Host, support USB host using a type A connector (J9, upper) USB C Host, support USB host using a type A connector (J9, lower) DBGU (RX and TX only) connected to a 9-way male RS connector (J) USART (RX, TX, RTS, CTS) connected to a 9-way male RS connector (J) USART (RX, TX, RTS, CTS) connected to a 9-way male RS connector (J) JTAG, 0 pin IDC connector (J9) MicroSD connector (J) SD/MMC connector (J) Headphone (J), line-in (J) Image sensor connector (J) DM board connection for QTouch and TFT LCD display with Touch Screen and backlight (J, J) DAA connecter RJ PC type (J) CAN bus connectors RJ PC type (CON, CON) ZigBee connector (J0) Three IO expansion ports (J, J, J) Test points, various test points are located throughout the board... Push Button Switches Reset, board reset (BP) Wake up, push button to bring the processor out of low power mode (BP) - Evaluation Kit (EK) User Guide A ATARM -Jul-

34 .. Function Blocks... Processor The Evaluation Kit board may be used with any of the Core Modules: SAM9G SAM9G SAM9G SAM9X SAM9X Evaluation Kit (EK) User Guide - A ATARM -Jul-

35 - Evaluation Kit (EK) User Guide A ATARM -Jul- Figure -. SODIMM Interface on EK Board PC0 NRST PB PB PA LCDDAT LCDDAT PD PA PA VDDNF LCDPCK PC PB ISI_D PD PC LCDDAT0 PD PC ENV_HDA# PA PA0 PD ETH0_RX- ONE_WIRE LCDDAT PB PD USBC_DM PB USBC_DP ISI_D E_CRSDV PA PC PD PC LCDDAT PC PC PA PB PC LCDDAT JTAG PC DIBN LCDDAT PC PC PC0 PB PB VDDNF PD PA ISI_D PD PB E_INTR PC LCDDAT LCDDEN DIBP ISI_D9 JP9 SIP LCDDAT PC PC PA PWR_EN R.k PD PC0 PA9 PA LCDDAT0 LCDDAT PC PC PC PA ISI_D PA (MCI_CD) RTS0 TXD0 PD9 RXD CTS TXD JP9 f or BMS Conf ig: When Open,BMS=: Boot on embedded ROM When Close,BMS=0: Boot on External memory RTS PA0 V PB PA PB PA0 LCDDAT9 LCDDAT PA PA PA0 LCDDAT9 PC9 PB PC9 PA PA LCDDAT ISI_PCK PD9 CANRX CANTX DRXD CANTX0 PB0 PA PA PA PD0 PC LCDDAT PC9 SELCONFIG PA PA PA PA LCDDAT PC PC PB PC9 PA ISI_HSYNC PB PB PD0 PD PD0 PD PD9 PB PB PC0 PA0 V SHDN PD ETH0_AVDDT PA E_TXCK DTXD E_RX0 E_RX PB0 E_TXEN E_TX0 E_TX E_RXER E_MDIO E_MDC LCDDAT PC PB PC PB PB PB PB PB PB AD_LR AD_YP AD0_XP PB PB PB AD_YM AD_XM PB PC TF RF TK TD RK RD PC PC LCDDAT E0_INTR ISI_VSYNC PA TDO PA0 BMS LCDDAT PD0 ISI_MCK PA PC ENV_HDC# LCDDAT PC PC PC PD OVCUR_USB PA9 ISI_D PA PC PC LCDDISP ETH0_GND PA0 PD VDDANA PC TWCK0 ISI_D LCDDAT PA PA PA9 PD PB (MCI0_DA) (MCI0_CDA) (MCI0_CK) (MCI0_DA0) (MCI0_DA) TDI (MCI0_DA) PD PD ETH0_TX+ PC PC ENV_HDB# PA PA VBUS_SENSE PC PC PA LCDPWM PA PC LCDDAT0 ISI_D PD PA0 VDDANA PB9 PD TCK PC PA9 PD PA PD PA9 PA LCDDAT VDDIOP ISI_D PC PC PD PC PB0 PC9 VBAT PD E0_RX E0_RXDV E0_RX0 TMS E0_TXEN E0_TX0 E0_TX E0_RXER E0_MDIO E0_MDC PA E0_TXCK PA PA PB PA PA (MCI_CDA) (MCI_CK) (MCI_DA0) (MCI_DA) (MCI_DA) (MCI_DA) ETH0_LED0 PA PC PB PB9 TWD0 ISI_D CANRX0 PC PC0 PD PC PA RTCK PA PB0 ETH0_RX+ USBB_DM PD PCK0 PC ISI_D0 PC0 PA USBB_DP PA LCDVSYNC VDDIOP PC PD ETH0_TX- LCDHSYNC PC ETH0_LED NTRST ISI_D0 PA9 PA ADVREF USBA_DP USBA_DM PA PB PA PC0 (MCI0_CD) PD0 PD PA SPI_MISO PC PC9 SPI_MOSI ZB_IRQ SPI_NPCS ZB_RSTN ZB_IRQ0 SPI_SPCK ZB_SLPTR PC0 WAKE UP ETH0_LED PC KEY CON - GND0 RFU RFU RFU 9 RFU GND RFU0 RFU 0 RFU 9 RFU RFU GND9 RFU0 0 RFU GND VCC VCC VCC VCC VBAT RFU9 9 RFU RFU RFU RFU GND RFU9 RFU RFU RFU RFU 0 RFU GND USBC_DP USBC_DM 9 GND 9 USBB_DP USBB_DM GND DIBP 9 DIBN GND USBA_DM USBA_DP GND 9 PD0/NANDOE PD/A/NANDALE PD/NCS PD/D 9 PD/D GND PD0/D0 PD/D PD/D 9 PD/D/A PD/D/A PD0/D0/NCS PA0/TXD0/SPI_NPCS 9 PA/RTS0/MCI_DA/E0_ETX0 9 PA/SCK0/MCI_DA/E0_ETXER 9 PA/SPI0_MISO/MCI_DA0 9 PA/SPI0_SPCK/MCI_CK 9 PA/RXD/SPI_NPCS0 0 PA/TIOA/SPI_SPCK 0 PA/TWCK0/SPI_NPCS/E0_ETXEN 0 PA/MCI0_CDA 09 PA/MCI0_DA PA0/MCI0_DA PA/TXD/CANTX PA0/DTXD/CANTX0 PA/TCLK/TF PA/TIOB0/RD PA9/TIOB/RF PC0/LCDDAT0/ISI_D0/TWD 9 PC/LCDDAT/ISI_D/TIOA PC/LCDDAT/ISI_D/TCLK PC/LCDDAT/ISI_D/TCLK PC9/LCDDAT9/ISI_D9/URXD0 9 PC/LCDDAT/ISI_D/PWM PC/LCDDAT/ISI_PCK/TIOA PC/LCDDAT/ISI_HSYNC/TCLK PC/LCDDAT/URXD 9 PC9/LCDDAT9/E_TX/PWM PC/LCDDAT/E_RX/PWM PC/LCDDAT/TXD PC/LCDDISP/RTS PC/LCDPWM/SCK 9 PC9/LCDDEN/E_TXCK/SCK PC/FIQ/E_MDIO/PCK PB0/E0_RX0/RTS 9 PB/E0_RXER/SCK PB/E0_TXCK/TWD PB/E0_MDC/AD PB/E0_TXER/AD9 PB9/E0_TX0/PCK/AD0 9 PB/E0_TX/PWM0/AD0 PB/E0_RX/PWM/AD PB/E0_RXCK/AD PB/E0_COL/AD PB/IRQ/ADTRG 9 PWR_EN 0 JTAGSEL WKUP 0 SHDN BMS nrst ntrst TDI 0 TCK TMS TDO RTCK RFU PD/NANDWE PD/A/NANDCLE PD/NWAIT PD/D 0 PD9/D9 PD/D PD/D PD/D/A0 0 PD/D/A PD9/D9/NCS PD/D/NCS PA/RXD0 90 PA/CTS0/MCI_DA/E0_ETX 9 PA/SPI0_MOSI/MCI_CDA 9 PA/SPI0_NPCS0 9 PA/TXD 00 PA/TIOA0/SPI_MISO 0 PA/TIOA/SPI_MOSI 0 PA0/TWD0/SPI_NPCS/E0_EMDC 0 PA/MCI0_DA0 0 PA/MCI0_CK 0 PA9/MCI0_DA PA/RXD/CANRX PA9/DRXD/CANRX0 PA/TCLK0/TK 0 PA/TCLK/TD PA/TIOB/RK PC/LCDDAT/ISI_D/TWCK 0 PC/LCDDAT/ISI_D/TIOB PC/LCDDAT/ISI_D/TIOA PC/LCDDAT/ISI_D/TIOB PC/LCDDAT/ISI_D/UTXD0 PC0/LCDDAT0/ISI_D0/PWM0 0 PC/LCDDAT/ISI_VSYNC/TIOB PC/LCDDAT/ISI_MCK PC/LCDDAT/E_RXER/UTXD PC/LCDDAT/E_TX0/PWM0 0 PC0/LCDDAT0/E_RX0/PWM PC/LCDDAT/RXD PC/CTS PC/LCDVSYNC/E_TXEN/RST 0 PC/LCDHSYNC/E_CRSDV/CTS PC0/LCDPCK/E_MDC PB/E0_RX/CTS 0 PB/E0_RXDV/SPI0_NPCS PB/E0_MDIO/TWCK PB/E0_TXEN/AD GNDANA PB0/E0_TX/PCK0/AD 0 PB/E0_TX/PWM/AD PB/E0_RX/PWM/AD PB/E0_CRS/AD GNDANA RFU RFU RFU VDDNF VDDNF NC _0 _ GND 99 GND 0 GND 9 GND GND GND GND9 GND0 GND GND GND 9 VDDIOP_0 VDDIOP_ VDDANA_0 VDDANA_ SELCONFIG ADVREF 90 ETH0_TX+ 9 ETH0_TX- 9 ETH0_RX+ 9 ETH0_RX- 99 LED0 9 LED 9 LED 9 AVDDT 9 GND_ETH 00 RXD0 CTS0 PC PD9

36 ... Power Supplies The EK Board features one adjustable LDO. It accepts DC V power input and outputs a regulated +.V to most other circuits on the board through four.v rails. VDDPIO0 VDDPIO VDDANA VDDISI This LDO is enabled through a dual FET scheme. The processor can assert SHDN (which is a VDDBUpowered I/O) to shut down the LDO to enter the so-called backup mode. The regulator on CM board is also shut down by the action of the SHDN signal. If the V battery is mounted on J, both CM and EK boards can be woken up by action on the BP button, which drives the WKUP signal (also a VDDBU-powered I/O). Figure -. EK Board Power Management V Q IRLML0 R 0k PWR_EN D BATCLTG JP SIP VDDANA VBAT C JP 00n VDDISI C u Place C near MN.pin R 0R D Red PWR_EN# C0 u V V POWER_EN V V R 00k R C 0u R 00k C u MN RT90A PGOOD EN VIN VDD GND ADJ NC VOUT VOUT = 0.V x (Rtop + Rbottom)/Rbottom C 0n R k k C u SIP FORCE POWER ON 9 EP C9 0u Q SiEDH V SHDN C0 p R 0k R 0k J C 00n L 0ohm at 00MHz L 0ohm at 00MHz L 0ohm at 00MHz L 0ohm at 00MHz VDDIOP Evaluation Kit (EK) User Guide - A ATARM -Jul-

37 There is another.v rail, VDDNF, supplied from the CM board. VDDNF is set to.v in the current CM design. The processors also support a.v NAND Flash device, in which case VDDNF is set to.v. In order to avoid potential voltage conflict on user-defined applications, a level shifter is inserted between the PIO lines on VDDNF rail and the.v application. Figure -9. Level Shifter For VDDNF Rail C PD PD PD0 PD9 PD 00n VDDNF MN VCCA VCCB DIR VCCB A OE A B 0 A B 9 A B A B 9 A B 0 A B A B GND B GND GND SNAVCTPWR V C9 ENV_HDC# ENV_HDB# ENV_HDA# 00n ZB_SLPTR ZB_RSTN... JTAG/ICE Software debug is accessed by a standard 0-pin JTAG connection. This allows connection to a standard USB-to-JTAG in-circuit emulator such as SAM-ICE. Figure -0. JTAG Interface R R R R9 J9 0 0 BR0-H k 00k DNP DNP R 00k 00k DNP DNP 0R DNP R0 R R 0R DNP 0R 0R NTRST TDI TMS TCK RTCK TDO NRST NTRST TDI TMS TCK RTCK TDO NRST - Evaluation Kit (EK) User Guide A ATARM -Jul-

38 ... DBGU The UART is connected to the DB-9 male socket through an RS- Transceiver (TXD and RXD only). A jumper, JP, is used to select DBGU or CAN0 between IO (PA9, PA0) sharing scheme. Close JP to select DBGU. Figure -. DBGU Com Port PA0 DTXD R9 00k R0 00k C0 00n C 00n MN C+ VCC C- C+ T GND V+ C- V- T C C C 00n 00n 00n 9 J PA9 DRXD R R 0R 0R R 0 9 R R 0R 0 SEL_CAN R 00k JP SIP EN SD ADMARW PWR_EN EARTH_RS Evaluation Kit (EK) User Guide - A ATARM -Jul-

39 ... USART The USART0 and USART are used as serial communication ports. Both USARTs are buffered with an RS- Transceiver (TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male socket. The software must assign the appropriate PIO pins to enable the USART function. The USART is only supported by SAM9G and SAM9X processors. The RS- Transceiver for USART is enabled by the signal SELCONFIG comprised of a pull down resistor on CM board. Ref to Section.. DM Board Overview for details. Figure -. USART Com Port USART0 PA PA0 PA PA RTS0 TXD0 CTS0 RXD0 R R R0 R R R k k 0R 0R 0R 0R R k C C.u 00n C 00n C 00n MN VCC GND V+ V- 9 SD EN TIN 9 TIN TIN 0 ROUT ROUT ROUT C+ 0 C- C+ C- C+ C- TOUT TOUT TOUT RIN RIN RIN C C C9 R9 00n 00n 00n 0R RTSC0 TXDC0 CTSC0 RXDC0 9 0 J L 0ohm at 00MHz ADMEARU EARTH_RS USART VDDIOP (only for SAM9G/SAM9X) SELCONFIG PC PC PC PC RTS TXD CTS RXD R R R9 R0 VDDIOP 0R 0R 0R 0R R k R k R k C C9.u 00n C 00n R C 00n k MN9 VCC GND V+ V- 9 SD EN TIN 9 TIN TIN 0 ROUT ROUT ROUT C+ 0 C- C+ C- C+ C- TOUT TOUT TOUT RIN RIN RIN C C C9 R 00n 00n 00n 0R RTSC TXDC CTSC RXDC 9 0 J ADMEARU EARTH_RS - Evaluation Kit (EK) User Guide A ATARM -Jul-

40 ... USB Ports The Evaluation Kit features three USB communication ports: Port A Port B Port C Host High Speed (EHCI) and Full Speed (OHCI) multiplexed with USB Device High speed Micro AB connector, J0 Host High Speed (EHCI) and Full Speed (OHCI) standard type A connector, J9 upper port Host Full speed OHCI only standard type A connector, J9 lower port All three USB Host ports are equipped with 00 ma high-side power switch for self-powered and buspowered applications. The USB device port features VBUS insert detection function through the resistor ladder R and R9. Refer to the embedded MPU product datasheet for detailed programming information. For datasheet reference numbers and titles, see Section. Applicable Documents. Figure -. USB Port (A) V USB A HOST/DEVICE INTERFACE V_INTER C0 00n C09 00n + C0 u + C0 u L 0ohm at 00MHz L C0 00n 0ohm at 00MHz V MN OUTA ENA IN FLGA GNG OUTB AIC-0GS FLGB ENB ACTIVE LOW OVCUR_USB ENV_HDA# R k PB LCD_DETECT# R k (VBUS_SENSE) PB V J0 C p R9 k R0 k EARTH_USB SHD VBUS DM DP ID GND (IDUSBA) USBA_DM USBA_DP G EARTH_USB Figure -. USB Port (B & C) USB HOST B&C INTERFACE USBB_DP USBB_DM J9 Dual USB A C0 00n C0 00n + C0 u + C0 u L 0ohm at 00MHz L 0ohm at 00MHz C0 00n V MN OUTA ENA IN FLGA GNG OUTB AIC-0GS FLGB ENB ENV_HDB# OVCUR_USB ENV_HDC# PB A A A A A B L 0ohm at 00MHz B B B B USBC_DM USBC_DP EARTH_USB EARTH_USB Evaluation Kit (EK) User Guide -9 A ATARM -Jul-

41 ... Ethernet 0/00 (EMAC) Port Except for SAM9G, the processor has two 0/00 Mbps Ethernet Mac Controllers. SAM9G SAM9G SAM9X SAM9G SAM9X EMAC RMII RMII MII MII + RMII The EK board is equipped with two Davicom DM9AEP PHYs for each Ethernet port. Both PHY Transceivers are configured as RMII mode. Both PHY transceivers have an RJ port with embedded transformer and three-status LEDs. By default, the ETH0 interface is implemented on the EK board. Additionally, for monitoring and control purposes, an LED functionality is carried on the RJ connectors to indicate activity, link, and speed status information for the respective ports. -0 Evaluation Kit (EK) User Guide A ATARM -Jul-

42 Figure -. ETH0 Port PB PB0 PB9 PB PB PB0 PB PB PB PB PB E0_TX E0_TX0 E0_TXEN E0_RX E0_RX0 E0_RXDV E0_RXER E0_MDC E0_MDIO E0_INTR R RR VDDANA Y OE 0MHz VDD VSS OUT VDDANA JP MN R0 0R REF_CLK/XT TXD 9 TXD 0 TXD TXD0 R0 0R DNP TX_EN TX_CLK/ISOLATE RXD/PHYAD RXD/PHYAD 9 RXD/PHYAD RXD0/PHYAD0 RX_CLK/0BTSER RX_DV/TESTMODE TX_ER/TXD RX_ER/RXD/RPTR COL/RMII R.k CRS/PHYAD MDC DM9AEP MDIO MDINTR 9 DISMDIX VDDANA DVDD DVDD DVDD DGND DGND DGND PWRDWN RESET XT TX+ RX- TX- RX+ BGRES LEDMODE LED0/OP0 LED/OP LED/OP CABLESTS/LINKSTS AVDDR AVDDR AVDDT 9 AGND AGND AGND BGRESG N.C E0_AVDDT C 00n R 0R E0_AVDDT VDDANA L0 00R EARTH_ETH0 ETH0_GND ETH0_GND R 0R R 0R EARTH_ETH0 ETH0_GND RJ ETHERNET CONNECTOR EARTH_ETH0 J J00DB TX+ R R R RR RR 0k C 00n ETH0 (Not available for SAM9G) RR 0k R0 0R VDDANA R 0R R 0R R 0R R 0R R 0R R 0R VDDANA R 0R DNP ETH0_LED R 0R DNP ETH0_LED R 0R DNP ETH0_LED0 R0 0R DNP ETH0_AVDDT R 0R DNP ETH0_TX+ R 0R DNP ETH0_TX- R 0R DNP ETH0_RX+ R 0R DNP ETH0_RX- RR 0k C 00n C 00n C9 00n C0 0u 0V RR9 0k R9 R R0 R R R R0 0k C 00n C 00n R.k FULL DUPLEX VDDANA L9 0ohm at 00MHz C 0u 0V R9 0R ETH0_GND C 00n R0 9.9R R09 9.9R R9 0R R0 9.9R R 9.9R C 00n C 0u 0V C 00n D Red R 0R Optional PHY Embedded on CM board Place close to J Optional PHY Embedded on CM board TD+ CT RD+ RX+ CT TD- TX- RD- RX- nf Left LED Right LED VDDANA 9 E0_TXCK NRST 0 R 0R R 0R Evaluation Kit (EK) User Guide - A ATARM -Jul-

43 Ethernet is only available for SAM9X. The PHY on Ethernet is enabled by the SELCONFIG signal from a pull-down resistor on the CM board. Refer to Section.. DM Board Overview for detail. Some pins (PC, PC0, PC, PC, PC and PC9) are configured as Ethernet input from PHY for SAM9X, whereas they are configured as LCD data pins on other processors. An IO buffer MN is inserted in series with these signals to prevent the LCD from being disturbed by unknown status of the PHY device. - Evaluation Kit (EK) User Guide A ATARM -Jul-

44 Figure -. ETH Port PC9 PC9 PC PC PC0 PC PC R RR E_TXCK E_TXCK E_TX E_TX0 E_TXEN MN VDDIOP C 00n SELCONFIG R RR0 SELCONFIG E_RX E_RX0 E_CRSDV E_RXER SELCONFIG E_TXCK PC PC0 PC PC E_INTR E_RX E_RX0 E_CRSDV E_RXER R RR ACSC VDDIOP E_MDC E_MDIO E_INTR E_INTR VDDIOP JP VDDIOP L0 0ohm at 00MHz SELCONFIG NRST EARTH_ETH GND_ETH VDDIOP VDDIOP Y OE VDD C 0MHz 00n VSS OUT R.k VDDIOP MN REF_CLK/XT TXD 9 TXD 0 TXD TXD0 TX_EN TX_CLK/ISOLATE RXD/PHYAD RXD/PHYAD RXD0/PHYAD0 9 RXD/PHYAD 9 RX_CLK/0BTSER RX_DV/TESTMODE TX_ER/TXD RX_ER/RXD/RPTR COL/RMII CRS/PHYAD MDC MDIO MDINTR DISMDIX DM9AEP XT TX+ RX- TX- RX+ AVDDR AVDDR AVDDT 9 AGND AGND AGND DVDD DVDD DVDD DGND DGND DGND PWRDWN RESET BGRESG BGRES LEDMODE LED0/OP0 LED/OP LED/OP CABLESTS/LINKSTS N.C R k E_AVDDT C9 00n R9 0R ETH (Only availabel for SAM9X) C9 00n GND_ETH RJ ETHERNET CONNECTOR EARTH_ETH E_AVDDT GND_ETH EARTH_ETH VDDIOP GND_ETH Right LED VDDIOP FULL DUPLEX D Red R9 0R RR 0k RR 0k RR 0k R 0R R 0R DNP RR 0k C00 0u 0V R 0R R 0R C9 00n C90 00n R0.k TD+ TX+ CT RD- RX- L E_AVDDT C9 R R 00n 00R 9.9R 9.9R TD- TX- RD+ RX+ CT C9 0u 0V C9 0u 0V 0 Left LED nf 9 R 0R OE 0 VCC I0 OE 9 O O0 I I O O I I O O I I 9 O O 0 I GND R0 0k C9 00n C99 00n C9 00n R R 9.9R 9.9R J J00DB C9 00n R 0R R 0R VDDIOP Evaluation Kit (EK) User Guide - A ATARM -Jul-

45 ... Audio The Evaluation Kit includes a WM CODEC for digital sound input and output. This interface includes audio jacks for line audio input (J) and headphone line output (J). The SAM9 processor is configured in IIS slave mode to interface with the WM Codec. The IIS master mode is also possible for evaluation by populating R/R and removing the crystal Y. Figure -. Audio Interface C 0p MN0 WMSEDS CLKOUT XTI/MCLK XTO MODE CSB SDIN SCLK OSC PB0 C p R R 0R LINE_IN PCK0 DNP STEREO_.mm J R DNP AUDIO_GND AUDIO_GND AUDIO_GND HEADPHONE C 0p AUDIO_GND L 0ohm at 00MHz STEREO_.mm J C9 u C u C p Y.MHz MODE = 0: -wire MPU mode for 9x TWI interface CSB = : addr=000 R 0k R 0k R.k R9.k DBVDD TWI_addr TWD0 TWCK0 C0 0u LOUT DCVDD C 0u ROUT C 00n VCC_DAC C 0u AVDD LLINEIN C0 00n HPVDD C 0u AUDIO_GND RLINEIN C 00n C 0u MICIN VMID C 00n MICBIAS AUDIO_GND R 0R RK BCLK PA R R TK RHPOUT DACDAT PA TD DACLRC PA TF ADCDAT PA R 0R RD LHPOUT ADCLRC PA R9 0R RF PA9 R.K R.K L 0ohm at 00MHz AGND HPGND DGND R R0 C 0p IIS of Audio Interface in Slave Mode C 0p.K.K AUDIO_GND L 0ohm at 00MHz VCC_DAC C 0u C 00n R 0R C 00n AUDIO_GND PA0 PA R near SODIMM R near CODEC AUDIO_GND AUDIO_GND C9 0uF/0V L 0ohm at 00MHz + C0 0uF/0V L 0ohm at 00MHz + R9 k R90 k AUDIO_GND C 0p AUDIO_GND C 00n C 0p C 00n - Evaluation Kit (EK) User Guide A ATARM -Jul-

46 ...9 -Wire EEPROM The EK board also features a -Wire device acting as a firmware label to store information like chip type, manufacturer s name, production date etc. Figure -. -Wire on EK VDDANA R.k PB ONE_WIRE R 0R MN I/O GND DSP NC NC NC NC...0 CAN Bus Two boards, the SAM9X-EK and SAM9X-EK, feature two Controller Area Network (CAN) ports with transceiver. CAN0 uses the same IOs (PA9, PA0) as the DBGU. A jumper, JP, is used to select either of the interfaces. Open JP to select the CAN function. Close JP to select the DBGU function. A -state output buffer, MN9 is inserted in series with the output channels of the CAN transceiver, which share IOs with the DBGU. This is necessary because the CAN transceiver does not feature -state outputs. Figure -9. CAN on EK (only for SAM9X/SAM9X) R 0k PA0 CANTX0 R0 0R SEL_CAN MN9 OE VCC PA9 CANRX0 A Y GND SNLVCGDBV MN RS D EN R CANH CANL VCC GND SNHVDDR JP C0 00n SIP C 0u R9 0R V V CON MJM00GE0-H CAN0 PA PA CANTX CANRX R R R R 0k 0R 0k 0R MN RS D EN R CANH CANL VCC GND SNHVDDR JP C 00n SIP C 0u R 0R V V CON MJM00GE0-H CAN Evaluation Kit (EK) User Guide - A ATARM -Jul-

47 ... Telephone Interface The Evaluation Kit features a smart DAA (Data Access Arrangement) chip to drive an analog telephone line on RJ PC port (J). Figure -0. Telephone Interface Q MMBAT Q MMBAT DIBN DIBP 0R can be replaced by bead to improve EMI C0 pf C 00n C 00n DAA_GND C 00n DAA_GND 00 R9.M 00 R9.M C 00n EIC R9 DAA_GND 00V C n RXI DAA_GND L 0ohm at 00MHz L9 0ohm at 00MHz R00 R0.0R.0R % % R0 9R % 0 C 0p C 0p R9 0R J D RJ TB00M--F MJM00GE0-H C 0pF TX LAN00-0 DAA_GND K C9 Q 0n MMBAT DAA_GND % 0 R9 R9 R9 0R 0R 0R % % % MN TEST PWR AVDD DIBN DIBP DVDD RAC TAC EIO 0 EIF 9 TXO TXF GPIO CX0-Z D MMBD00S--F VC EP C 0pF DVDD C 00n DAA_GND R99 00R R0 0R D MMBD00S--F R 0R R 0R DAA_GND Q MMBAT - Evaluation Kit (EK) User Guide A ATARM -Jul-

48 ... SD/MMC Interface The Evaluation Kit has two high-speed MultiMedia Card Interfaces (MCI). The first interface is used as a -bit interface (MCI0), connected to a MicroSD card slot. The second interface is used as a -bit interface (MCI), connected to an SD/MMC card slot. The memory card is not included in the Evaluation Kit. Please note that the power is connected to VCC, which is. volts. Figure -. SD/MMC Interface VDDNF R9 0k R0 R R R k k k k R 0k PD PA PA PA PA PA0 PA9 (MCI0_CD) (MCI0_DA) (MCI0_DA0) (MCI0_CK) (MCI0_CDA) (MCI0_DA) (MCI0_DA) RR R RR R C 00n J 0 SW SW 9 Micro SD PJS VDDNF JP SIP R R R R k k k k RR 0k PD PA PA PA PA PA PA (MCI_WP) (MCI_CD) (MCI_DA) (MCI_DA0) (MCI_CK) (MCI_CDA) (MCI_DA) (MCI_DA) RRR RR R V C 00n J 9 DAT DAT0 VSS CLK VDD VSS CMD DAT DAT SDCN-B0-00-F CD WP GND GND SH SH 0 Evaluation Kit (EK) User Guide - A ATARM -Jul-

49 ... ZigBee The EK board has a 0-pin male connector for the Atmel RZ00 ZigBee module. DNP 0 Ohm resistors have been implemented in series with the PIO lines that are used elsewhere in the design. Thereby, enable their individual disconnections, should a conflict occur in user application. Figure -. ZigBee Interface ZB_RSTN PA PA0 PA PD ZB_IRQ SPI_NPCS SPI_MISO DNP DNP DNP DNP R R R R 0R 0R 0R 0R J0 9 0 HDX0 R R C p DNP DNP 0R 0R C.n ZB_IRQ0 PD SPI_MOSI SPI_SPCK V JP0 C DNP DNP.u PA ZB_SLPTR PA PA... LED Indicators The EK board has three LED indicators for purposes shown below: Table -. LED Indicators Reference Color Function D Red v Power indicator D Red ETH0 Full Duplex D Red ETH Full Duplex Refer to Section... Power Supplies and Section... Ethernet 0/00 (EMAC) Port for details.... Expansion Ports Most GPIOs are routed to expansion ports J, J, J. All I/Os of the MPU Image Sensor Interface (ISI) are routed to connectors J. The LCD and touch screen interfaces are routed to connectors J, J. Figure -. I/O Expansion V V V V V V JP JP JP V PA0 PA PA PA PA PA PA PA PA PA9 PA0 PA PA PA PA PA J HDX0-HH PA PA PA PA9 PA0 PA PA PA PA PA PA PA PA PA9 PA0 PA V V PC0 PC PC PC PC PC PC PC PC PC9 PC0 PC PC PC PC PC J HDX0-HH PC PC PC PC9 PC0 PC PC PC PC PC PC PC PC PC9 PC0 PC V V PB0 PB PB PB PB PB PB PB PB PB9 PB0 PB PB PB PB PB J HDX0-HH PB PB PB PD PD PD PD PD PD9 PD0 PD V - Evaluation Kit (EK) User Guide A ATARM -Jul-

50 Figure -. LCD and ISI Expansion V_LCD R 0R DNP R 0R DNP CHANGE# V J ZB_IRQ0 TWCK0 9 0 LCDDAT 9 0 LCDDAT LCDDAT LCDDAT LCDDAT9 LCDDAT 9 0 TWD0 LCDDAT LCDDAT LCDDAT LCDDAT LCDDAT0 LCDDAT LCDDAT LCDDAT LCDDAT LCDDAT0 TSM--0-L-DV-A SELCONFIG R V_INTER J LCDDAT LCDDAT LCDDAT0 9 0 LCDDAT LCDDISP LCDVSYNC LCDDEN 9 0 AD0_XP AD_YP AD_LR 0R TSM-0-0-L-DV-A LCDDAT LCDDAT9 LCDDAT LCDDAT LCDPWM LCDHSYNC LCDPCK AD_XM AD_YM R9 0R ONE_WIRE LCD_DETECT R 0R.. Configuration This section describes the PIO usage, the jumpers, the test points and the solder drops of the EK board.... JTAG/ICE Configuration Table -9. JTAG/ICE Designation Default Setting Feature R0 Not Populated Disables the ICE NTRST input R Populated Enables the ICE RTCK return. R9 must be opened R Populated Enables the ICE NRST input R Not Populated Disables TCK <-> RTCK local loop... Boot Mode Select Configuration Table -0. BMS Designation Default Setting Feature JP9 Open Default to boot on embedded ROM Close to boot on external memory Evaluation Kit (EK) User Guide -9 A ATARM -Jul-

51 ... Force Power ON Configuration Table -. Force Power ON Designation Default Setting Feature JP Close Keep on-board regulator always on Open to feature SHDN function... White Protection Configuration on MCI Table -. Write Protection on MCI Designation Default Setting Feature JP Close MCI write protect selected Open to disable protection... Selection between DBGU and CAN Table -. Select DBGU or CAN Designation Default Setting Feature JP Close Default to select DBGU Open to select CAN0... Codec IIS Configuration Table -. Codec IIS Designation Default Setting Feature R, R Not Populated IIS master mode, clock the codec by PCK0 C, C, Y Populated IIS slaver mode, clock the codec by external crystal... ETH0 Configuration Table -. ETH0 Designation Default Setting Feature R0, R, R, R, R, R, R, R, R R, R, R9, R, R, R, R, R, R Not Populated Populated Populated to select the PHY channel on CM. Channel on EK must be cut if select the PHY on CM. Selection of PHY channel on EK -0 Evaluation Kit (EK) User Guide A ATARM -Jul-

52 ... PIO Usage Table -. PIO A Pin Assignment and Signal Description Signal Alternate Periph A Periph B Periph C PA0 TXD0 SPI_NPCS TXD0/ ZigBee USART0 shared with ZigBee PA RXD0 SPI0_NPCS RXD0 USART0 PA RTS0 MCI_DA E0_ETX0 RTS0/ MCI USART0 shared with MCI PA CTS0 MCI_DA E0_ETX CTS0/ MCI USART0 shared with MCI PA SCK0 MCI_DA E0_ETXER MCI PA TXD CANTX CAN PA RXD CANRX CAN PA TXD SPI0_NPCS ZB_IRQ0 PA RXD SPI_NPCS0 DataFlash PA9 CANRX0 DBGU+CAN0 DBGU shared with CAN0 PA0 CANTX0 DBGU+CAN0 DBGU shared with CAN0 PA SPI0_MISO MCI_DA0 MCI PA SPI0_MOSI MCI_CDA MCI PA SPI0_SPCK MCI_CK MCI ZB_IRQ PA SPI0_NPCS0 MCI0 PA MCI0_DA0 MCI0 PA MCI0_CDA MCI0 PA MCI0_CK MCI0 PA MCI0_DA MCI0 PA9 MCI0_DA MCI0 PA0 MCI0_DA DataFlash PA TIOA0 SPI_MISO ZigBee DataFlash PA TIOA SPI_MOSI ZigBee DataFlash PA TIOA SPI_SPCK ZigBee SSC PA TCLK0 TK SSC PA TCLK TF SSC PA TCLK TD SSC PA TIOB0 RD SSC PA TIOB RK SSC PA9 TIOB RF SSC PA0 TWD0 SPI_NPCS E0_EMDC TWD0 PA TWCK0 SPI_NPCS E0_ETXEN TWCK0 Evaluation Kit (EK) User Guide - A ATARM -Jul-

53 Table -. PIO B Pin Assignment and Signal Description Signal Alternate Periph A Periph B Periph C Module CM EK PB0 E0_RX0 RTS ETH0 PB E0_RX CTS ETH0 PB E0_RXER SCK ETH0 PB E0_RXDV SPI0_NPCS ETH0 PB E0_TXCK TWD ETH0 PB E0_MDIO TWCK ETH0 PB AD E0_MDC ETH0 PB AD E0_TXEN ETH0 PB AD9 E0_TXER ETH0_INTR PB9 AD0 E0_TX0 PCK ETH0 PB0 AD E0_TX PCK0 ETH0 PB AD0xp E0_TX PWM0 TSC PB ADxm E0_TX PWM TSC PB ADyp E0_RX PWM TSC PB ADym E0_RX PWM TSC PB ADlr E0_RXCK TSC PB AD E0_CRS VBUS_SENSE (USB) PB AD E0_COL OVCUR_USB (Open drain) PB IRQ ADTRG USER_LED# ONE_WIRE - Evaluation Kit (EK) User Guide A ATARM -Jul-

54 Table -. PIO C Pin Assignment and Signal Description Signal Alternate Periph A Periph B Periph C EK f (LCD) EK f (ISI+IO) PC0 LCDDAT0 ISI_D0 TWD LCDDAT0 ISI_D0 PC LCDDAT ISI_D TWCK LCDDAT ISI_D PC LCDDAT ISI_D TIOA LCDDAT ISI_D PC LCDDAT ISI_D TIOB LCDDAT ISI_D PC LCDDAT ISI_D TCLK LCDDAT ISI_D PC LCDDAT ISI_D TIOA LCDDAT ISI_D PC LCDDAT ISI_D TIOB LCDDAT ISI_D PC LCDDAT ISI_D TCLK LCDDAT ISI_D PC LCDDAT ISI_D UTXD0 LCDDAT ISI_D PC9 LCDDAT9 ISI_D9 URXD0 LCDDAT9 ISI_D9 PC0 LCDDAT0 ISI_D0 PWM0 LCDDAT0 ISI_D0 PC LCDDAT ISI_D PWM LCDDAT ISI_D PC LCDDAT ISI_PCK TIOA LCDDAT ISI_PCK PC LCDDAT ISI_VSYNC TIOB LCDDAT ISI_VSYNC PC LCDDAT ISI_HSYNC TCLK LCDDAT ISI_HSYNC PC LCDDAT ISI_MCK PCK0 SSC LCDDAT ISI_MCK/PCK0 PC LCDDAT E_RXER UTXD LCDDAT E_RXER PC LCDDAT URXD LCDDAT PC LCDDAT E_TX0 PWM0 LCDDAT E_TX0 PC9 LCDDAT9 E_TX PWM LCDDAT9 E_TX PC0 LCDDAT0 E_RX0 PWM LCDDAT0 E_RX0 PC LCDDAT E_RX PWM LCDDAT E_RX PC LCDDAT TXD LCDDAT TXD PC LCDDAT RXD LCDDAT RXD PC LCDDISP RTS LCDDISP RTS PC CTS CTS PC LCDPWM SCK Eth_Intr LCDPWM PC LCDVSYNC E_TXEN RTS LCDVSYNC E_TXEN PC LCDHSYNC E_CRSDV CTS LCDHSYNC E_CRSDV PC9 LCDDEN E_TXCK SCK LCDDEN E_TXCK PC0 LCDPCK E_MDC LCDPCK E_MDC PC FIQ E_MDIO PCK E_MDIO Evaluation Kit (EK) User Guide - A ATARM -Jul-

55 Table -9. PIO D Pin Assignment and Signal Description Signal Alternate Periph A Periph B Periph C Module CM EK PD0 NANDOE Nand Flash PD NANDWE Nand Flash PD A/NANDALE Nand Flash PD A/NANDCLE Nand Flash PD NCS CS NAND Flash PD NWAIT NAND_RD/BY PD D Nand Flash PD D Nand Flash PD D Nand Flash PD9 D9 Nand Flash PD0 D0 Nand Flash MCI0_CD (switch) PD D Nand Flash MCI_CD (switch) PD D Nand Flash ZB_RSTN PD D Nand Flash ZB_SLPTR PD D ENV_HDA# PD D A0 ENV_HDB# PD D A ENV_HDC# PD D A PD D A PD9 D9 NCS PD0 D0 NCS PD D NCS POWR_LED - Evaluation Kit (EK) User Guide A ATARM -Jul-

56 .. Connectors... Power Supply Figure -. Power Supply Connector J Table -0. Power Supply Connector J Signal Description Pin Mnemonic Signal description Center +V GND Floating... SODIMM Card Edge Socket The Evaluation Kit uses a SODIMM00 standard connector for CM board interfacing. Please note that this is not an industry standard pin-out and that it is unlikely to be compatible with offthe-shelf SODIMM cards. Figure -. SODIMM00 Socket CON Table -. SODIMM00 CON Signal Descriptions Function Type x pad name SODIMM 00 x pad name Type Function Front Side A B Back Side VCC V POWER OUTPUT POWER OUTPUT VCC V VCC V POWER OUTPUT POWER OUTPUT VCC V GND POWER OUTPUT VBAT USBC_DP I/O USB Data Positive SYSC JTAGSEL USBC_DM I/O USB Data Negative 9 0 SYSC WKUP GND SYSC SHDN Evaluation Kit (EK) User Guide - A ATARM -Jul-

57 Table -. SODIMM00 CON Signal Descriptions (Continued) Function Type x pad name SODIMM 00 x pad name Type Function USBB_DM I/O USB Data Negative SYSC BMS USBB_DP I/O USB Data Positive SYSC nrst GND SYSC ntrst DIBP I/O 9 0 RSTJTAG TDI DIBN I/O RSTJTAG TCK GND RSTJTAG TMS USBA_DM I/O USB Data Negative RSTJTAG TDO USBA_DP I/O USB Data Positive RSTJTAG RTCK GND 9 0 PWR_EN RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU KEY GND GND RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU GND GND RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU VDDNF POWER DOMAIN FROM CM POWER DOMAIN FROM CM VDDNF PD0 GPIO D NANDOE NANDWE GPIO D PD PD GPIO D A/NANDALE A/NANDCLE GPIO D PD PD GPIO D NCS NWAIT GPIO D PD PD GPIO D D 9 0 D GPIO D PD PD GPIO D D D9 GPIO D PD9 GND GND PD0 GPIO D D0 D GPIO D PD PD GPIO D D D GPIO D PD PD GPIO D D 9 0 D/A0 GPIO D PD PD GPIO D D/A D/A GPIO D PD PD GPIO D D/A D9/NCS GPIO D PD9 - Evaluation Kit (EK) User Guide A ATARM -Jul-

58 Table -. SODIMM00 CON Signal Descriptions (Continued) Function Type x pad name SODIMM 00 x pad name Type Function USBB_DM I/O USB Data Negative SYSC BMS USBB_DP I/O USB Data Positive SYSC nrst GND SYSC ntrst DIBP I/O 9 0 RSTJTAG TDI DIBN I/O RSTJTAG TCK GND RSTJTAG TMS USBA_DM I/O USB Data Negative RSTJTAG TDO USBA_DP I/O USB Data Positive RSTJTAG RTCK GND 9 0 PWR_EN RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU KEY GND GND RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU GND GND RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU VDDNF POWER DOMAIN FROM CM POWER DOMAIN FROM CM VDDNF PD0 GPIO D NANDOE NANDWE GPIO D PD PD GPIO D A/NANDALE A/NANDCLE GPIO D PD PD GPIO D NCS NWAIT GPIO D PD PD GPIO D D 9 0 D GPIO D PD PD GPIO D D D9 GPIO D PD9 GND GND PD0 GPIO D D0 D GPIO D PD PD GPIO D D D GPIO D PD PD GPIO D D 9 0 D/A0 GPIO D PD PD GPIO D D/A D/A GPIO D PD PD GPIO D D/A D9/NCS GPIO D PD9 Evaluation Kit (EK) User Guide - A ATARM -Jul-

59 Table -. SODIMM00 CON Signal Descriptions (Continued) Function Type x pad name SODIMM 00 x pad name Type Function USBB_DM I/O USB Data Negative SYSC BMS USBB_DP I/O USB Data Positive SYSC nrst GND SYSC ntrst DIBP I/O 9 0 RSTJTAG TDI DIBN I/O RSTJTAG TCK GND RSTJTAG TMS USBA_DM I/O USB Data Negative RSTJTAG TDO USBA_DP I/O USB Data Positive RSTJTAG RTCK GND 9 0 PWR_EN RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU KEY GND GND RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU GND GND RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU 9 0 RFU RFU VDDNF POWER DOMAIN FROM CM POWER DOMAIN FROM CM VDDNF PD0 GPIO D NANDOE NANDWE GPIO D PD PD GPIO D A/NANDALE A/NANDCLE GPIO D PD PD GPIO D NCS NWAIT GPIO D PD PD GPIO D D 9 0 D GPIO D PD PD GPIO D D D9 GPIO D PD9 GND GND PD0 GPIO D D0 D GPIO D PD PD GPIO D D D GPIO D PD PD GPIO D D 9 0 D/A0 GPIO D PD PD GPIO D D/A D/A GPIO D PD PD GPIO D D/A D9/NCS GPIO D PD9 - Evaluation Kit (EK) User Guide A ATARM -Jul-

60 Table -. SODIMM00 CON Signal Descriptions (Continued) Function Type x pad name SODIMM 00 x pad name Type Function PD0 GPIO D D0/NCS D/NCS GPIO D PD POWER OUTPUT POWER OUTPUT PA0 GPIO A TXD0/SPI-NPCS 9 90 RXD0/SPI0-NPCS GPIO A PA PA GPIO A MCI_DA/E0_ETX0 9 9 PA PA PA GPIO A GPIO A GPIO A SCK0/MCI_DA/ E0_ETXER SPI0_MISO/ MCI_DA0 SPI0_SPCK/ MCI_CK CTS0/ MCI_DA/ E0_ETX GPIO A PA 9 9 GND 9 9 SPI0_MOSI/ MCI_CDA GPIO A PA 9 9 SPI0_NPCS0 GPIO A PA GND TXD/ SPI0_NPCS GPIO A PA PA GPIO A RXD/SPI_NPCS0 0 0 TIOA0 /SPI_MISO GPIO A PA PA GPIO A TIOA/SPI_MOS 0 0 PA GPIO A TWCK0/SPI_NPCS/ E0_ETXEN 0 0 TIOA/ SPI_SPCK TWD0/ SPI_NPCS/ E0_EMDC GPIO A GPIO A GND 0 0 MCI0_DA0 GPIO A PA PA GPIO A MCI0_CDA 09 0 MCI0_CK GPIO A PA PA GPIO A MCI0_DA MCI0_DA GPIO A PA9 PA0 GPIO A MCI0_DA GND PA GPIO A TXD/CANTX RXD/CANRX GPIO A PA PA0 GPIO A DTXD/CANTX0 DRXD/CANRX0 GPIO A PA9 GND 9 0 TCLK0/TK GPIO A PA PA GPIO A TCLK/TF TCLK/TD GPIO A PA PA GPIO A TIOB0/RD TIOB/RK GPIO A PA PA9 GPIO A TIOB/RF GND VDDIOP POWER OUTPUT POWER OUTPUT VDDIOP PC0 GPIO C LCDDAT0/ISI_D0 9 0 LCDDAT GPIO C PC PC GPIO C LCDDAT/ISI_D LCDDAT GPIO C PC PC GPIO C LCDDAT LCDDAT GPIO C PC GND LCDDAT GPIO C PC PC GPIO C LCDDAT LCDDAT GPIO C PC PC9 GPIO C LCDDAT9 9 0 LCDDAT0 GPIO C PC0 PC GPIO C LCDDAT GND PC GPIO C LCDDAT LCDDAT GPIO C PC PC GPIO C LCDDAT LCDDAT GPIO C PC GND LCDDAT GPIO C PC PA PA0 Evaluation Kit (EK) User Guide -9 A ATARM -Jul-

61 Table -. SODIMM00 CON Signal Descriptions (Continued) Function Type x pad name SODIMM 00 x pad name Type Function PC GPIO C LCDDAT 9 0 LCDDAT GPIO C PC PC9 GPIO C LCDDAT9 LCDDAT0 GPIO C PC0 PC GPIO C LCDDAT GND PC GPIO C LCDDAT LCDDAT GPIO C PC PC GPIO C LCDDISP GPIO C PC PC GPIO C LCDPWM 9 0 LCDVSYNC GPIO C PC GND LCDHSYNC GPIO C PC PC9 GPIO C LCDDEN E_MDC GPIO C PC0 PC GPIO C E_MDIO SELCONFIG VDDANA POWER OUTPUT POWER OUTPUT VDDANA PB0 GPIO B E0_RX0 9 0 E0_RX GPIO B PB PB GPIO B E0_RXER E0_RXDV GPIO B PB PB GPIO B E0_TXCK E0_MDIO GPIO B PB PB GPIO B E0_MDC E0_TXEN GPIO B PB PB GPIO B E0_TXER GNDANA PB9 GPIO B E0_TX0 9 0 E0_TX GPIO B PB0 PB GPIO B E0_TX E0_TX GPIO B PB PB GPIO B E0_RX E0_RX GPIO B PB PB GPIO B E0_RXCK E0_CRS GPIO B PB PB GPIO B E0_COL GNDANA PB GPIO B IRQ 9 90 POWER OUTPUT POWR_REF GND 9 9 ETH LED0 ETH0_TX+ ETH 9 9 ETH LED ETH0_TX- ETH 9 9 ETH LED ETH0_RX+ ETH 9 9 ETH AVDDT ETH0_RX- ETH GND_ETH... JTAG/ICE Connector Figure -. JTAG J9-0 Evaluation Kit (EK) User Guide A ATARM -Jul-

62 Table -. JTAG/ICE Connector J Signal Descriptions Pin Mnemonic Description VTref..V power This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor. Vsupply..V power ntrst TARGET RESET - Active-low output signal that resets the target GND Common ground TDI TEST DATA INPUT - Serial data output line, sampled on the rising edge of the TCK signal. GND Common ground TMS TEST MODE SELECT GND Common ground 9 TCK TEST CLOCK - Output timing signal, for synchronizing test logic and control register access. 0 GND Common ground RTCK - Input Return test clock signal from the target. GND Common ground This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system. JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to ntrst on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection. JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU. JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal. JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND. TDO JTAG TEST DATA OUTPUT - Serial data input from the target. JTAG data output from target CPU. Typically connected to TDO on target CPU. GND Common ground nsrst RESET Active-low reset signal. Target CPU reset signal. GND Common ground RFU This pin is not connected in SAM-ICE. GND Common ground 9 RFU This pin is not connected in SAM-ICE. 0 GND Common ground Evaluation Kit (EK) User Guide - A ATARM -Jul-

63 ... USB Type A Dual Port Figure -. USB Type A Dual Port J9 Table -. USB Type A Dual Port J9 Signal Descriptions Pin Mnemonic Description A Vbus USB_A V power A DM USB_A Data minus A DP USB_A Data plus A GND Common ground B Vbus USB_A V power B DM USB_A Data minus B DP USB_A Data plus B GND Common ground Mechanical pins Shield - Evaluation Kit (EK) User Guide A ATARM -Jul-

64 ... USB Micro AB Figure -9. USB USB Host/Device Micro AB Connector J0 Table -. USB USB Host/Device Micro AB Connector J0 Signal Descriptions Pin Mnemonic Description Vbus v power DM Data minus DP Data plus ID On the Go Identification GND Common ground... DBGU Figure -0. DBGU Connector J Table -. DBGU Connector J Signal Descriptions Pin Mnemonic Description,,, 9 NO CONNECTION RXD (RECEIVED DATA) RS serial data output signal TXD (TRANSMITTED Data) RS serial data input signal GND Common ground RTS (REQUEST TO SEND) NO USED CTS (CLEAR TO SEND) NO USED Mechanical pins Shield Evaluation Kit (EK) User Guide - A ATARM -Jul-

65 ... RS Connector with RTS/CTS Handshake Support Figure -. USART Connector J, J Table -. USART Connector J Signal Descriptions Pin Mnemonic Description,,, 9 NO CONNECTION RXD (RECEIVED DATA) PA RS serial data output signal TXD (TRANSMITTED Data) PA0 RS serial data input signal GND Common ground RTS (REQUEST TO SEND) PA Active-positive RS input signal CTS (CLEAR TO SEND) PA Active-positive RS output signal Mechanical pins Shield Table -. USART Connector J Signal Descriptions Pin Mnemonic Description,,, 9 NO CONNECTION RXD (RECEIVED DATA) PC RS serial data output signal TXD (TRANSMITTED Data) PC RS serial data input signal GND Common ground RTS (REQUEST TO SEND) PC Active-positive RS input signal CTS (CLEAR TO SEND) PC Active-positive RS output signal Mechanical pins Shield - Evaluation Kit (EK) User Guide A ATARM -Jul-

66 ... DAA RJ Socket (PC) Figure -. DAA RJ Socket J Table -. DAA RJ Socket J Signal Descriptions Pin Mnemonic Description,,, NO CONNECTION RAC RING side of ordinary telephone line TAC TIP side of ordinary telephone line...9 CAN RJ Socket (PC) Figure -. CAN RJ Socket CON, CON Table -9. DAA RJ Socket J Signal Descriptions Pin Mnemonic Description V POWER PIN V POWER PIN CANL CAN bus differential pair CANH CAN bus differential pair, GND Common ground Evaluation Kit (EK) User Guide - A ATARM -Jul-

67 ...0 MicroSD MCI0 Figure -. MicroSD Socket J Table -0. MicroSD Socket J Signal Descriptions Pin Mnemonic Description DAT Data Bit CD/DAT Card Detect/Data Bit CMD Command Line VCC Supply Voltage.V CLK Command Line VSS Common ground DAT0 Data Bit 0 DAT Data Bit 9 SW No use, grounded 0 CARD DETECT CARD DETECT... SD/MMC MCI Figure -. SD/MMC Socket J Table -. SD Socket J Signal Descriptions Signal Pin Mnemonic PIO SD Card MMC Card -Bit Mode -Bit Mode MCI_DA PA Not Used Read Wait (RW) Data Line DAT or Read Wait (RW) MCI_DA PA Reserved Not Used Data Line DAT MCI_CDA PA Command/Response Supply Voltage (.-volts) - Evaluation Kit (EK) User Guide A ATARM -Jul-

68 Table -. SD Socket J Signal Descriptions (Continued) Signal Pin Mnemonic PIO SD Card MMC Card -Bit Mode -Bit Mode MCI_CK PA Clock GND Ground MCI_DA0 PA Data Line DAT0 MC_DA PA Not Used Interrupt (IRQ) Data Line DAT or Interrupt (IRQ) 9 GND Ground 0 MCI_CD PD Card Detect, configured as GPIO, Power domain VDDNF WP Write Protect Detect, connects to jumper JP GND Ground GND Ground GND Ground GND Ground... Ethernet RJ Socket J, J Figure -. Ethernet RJ Socket J, J Table -. DAA RJ Socket J Signal Descriptions Pin Mnemonic Description TX+ DIFFERENTIAL OUTPUT PLUS TX- DIFFERENTIAL OUTPUT MINUS RX+ DIFFERENTIAL INPUT PLUS Reserved Reserved DIFFERENTIAL INPUT MINUS RX- Reserved Reserved Evaluation Kit (EK) User Guide - A ATARM -Jul-

69 ... ZigBee Socket J0 Figure -. ZigBee Socket J0 Table -. ZigBee Socket J0 Signal Descriptions Function Signal Name Port Pin Pin Port Signal Name Reset /RST Misc. Function Interrupt Request IRQ SLP_TR SLP_TR SPI chip select /SEL MOSI SPI MOSI SPI MISO MISO SCLK SPI CLK Power Supply GND GND 9 0 VCC VCC VCC Option on misc. port set by OR or solder shunts EEprom for MAC address, cap array settings and serial number TST: test mode activation CLKM: RF chip clock output Voltage range:.v to.v, regulated to.v... LCD/ISI Socket J Figure -. LCD/ISI Socket J Table -. LCD/ISI Socket J Signal Descriptions LCD ISI Pin Num Pin Num ISI LCD V V GND GND VDDISI VDDISI GND GND ZB_IRQ0 ZB_IRQ0 ZB_IRQ TWCK0 TWCK0 TWD0 GND GND 9 0 ISI_MCK LCDDAT GND GND ISI_VSYNC LCDDAT GND GND ISI_HSYNC LCDDAT - Evaluation Kit (EK) User Guide A ATARM -Jul-

70 Table -. LCD/ISI Socket J Signal Descriptions (Continued) LCD ISI Pin Num Pin Num ISI LCD GND GND ISI_PCK LCDDAT GND GND ISI_D0 LCDDAT0 LCDDAT ISI_D 9 0 ISI_D LCDDAT LCDDAT ISI_D ISI_D LCDDAT LCDDAT ISI_D ISI_D LCDDAT LCDDAT ISI_D ISI_D LCDDAT LCDDAT9 ISI_D9 ISI_D0 LCDDAT0 LCDDAT ISI_D 9 0 GND GND... LCD/TSC Socket J Figure -9. LCD/TSC Socket J Table -. LCD/TSC Socket J Signal Descriptions LCD Pin Num Pin Num LCD V V_INTER GND GND V V_INTER GND GND LCDDAT LCDDAT LCDDAT LCDDAT9 LCDDAT0 9 0 LCDDAT LCDDAT LCDDAT GND GND GND GND LCDDISP LCDPWM LCDCSYNC LCDHSYNC LCDDEN 9 0 LCDPCK GND GND GND GND AD0_XP TSC TSC AD_XM AD_YP TSC TSC AD_YM AD_LR TSC ONE_WIRE GND GND 9 0 GND GND SPI_MISO SPI_MOSI SPI_SPCK SPI_NPCS EN_PWRLCD SELCONFIG LCD_DETECT LCD_DETECT# PD PD GND GND 9 0 GND GND Evaluation Kit (EK) User Guide -9 A ATARM -Jul-

71 ... IO Expansion Port J Figure -0. IO Expansion Socket J Table -. Expansion Socket J Signal Descriptions PIO Power Pin Num Pin Num Power PIO V, or V V, or V GND GND PA0 PA PA PA PA 9 0 PA PA PA9 PA PA0 PA PA PA PA PA 9 0 PA PA PA PA9 PA PA0 PA PA PA PA 9 0 PA PA PA9 PA PA0 PA PA GND GND V 9 0 V -0 Evaluation Kit (EK) User Guide A ATARM -Jul-

72 ... IO Expansion Port J Figure -. IO Expansion Socket J Table -. Expansion Socket J Signal Descriptions PIO Power Pin Num Pin Num Power PIO V, or V V, or V GND GND PC0 PC PC PC PC 9 0 PC PC PC9 PC PC0 PC PC PC PC PC 9 0 PC PC PC PC9 PC PC0 PC PC PC PC 9 0 PC PC PC9 PC PC0 PC PC GND GND V 9 0 V Evaluation Kit (EK) User Guide - A ATARM -Jul-

73 ... IO Expansion Port J Figure -. IO Expansion Socket J Table -. Expansion Socket J Signal Descriptions PIO Power Pin Num Pin Num Power PIO V, or V V, or V GND GND PB0 PB PB PB PB 9 0 PB PB - PB - PB - PB - PB PB PD PB9 PD PB0 PD PB PD PB 9 0 PD PB PD9 PB PD0 PB PD GND GND V 9 0 V - Evaluation Kit (EK) User Guide A ATARM -Jul-

74 B A Evaluation Kit Hardware.. Schematics Figure -. EK Board Schematics Sheet V POWER SUPPLY Sheet Sheet ANALOG Battery V INPUT V HE0 RJ USBA USBB USBC VBAT ICE SmartDAA D HOST & DEVICE HOST HOST INTERFACE D Sheet Sheet 9 ANALOG Reference V Sheet USB A,B,C ICE RS SmartDAA DBGU COM USER INTERFACE COM ONE WIRE EEPROM Sheet C C HE HE Sheet RJ LCD CAN0 INTERFACE ISI Sheet CAN S O D I M M C O N N E C T O R HE0 ZIGBEE INTERFACE PIO A,...D PIO A,...D Sheet 0/00 FAST 0/00 FAST EHT AUDIO ETH0 IN OUT PIO A RJ RJ B B Sheet 0 Sheet Sheet PIO CONNECTOR PIO C MMC SD SDIO CARD READER PIO CONNECTOR MMC SD SDIO CARD READER PIO B&D PIO CONNECTOR Sheet Sheet A A Derek -Oct-0 X.X XX-XXX-XX Derek 0-JUN-0 X.X XX-XXX-XX DES. DATE VER. DATE MODIF. REV AT9SAM9x-EK / SCALE REV. SHEET B BLOCK Diagram Evaluation Kit (EK) User Guide - A ATARM -Jul-