Spark-501 Standard SMARC, Cortex-A5 based System on Module Integration guide

Transcription

1 Spark-501 Standard SMARC, Cortex-A5 based System on Module Integration guide Revision 1.1

2 Contents 1 Scope SoM introduction SoM models SPARK-501 Integration guide Block diagram Power connectivity Reset Spark-501 System Cortex-A5 Processor Memories Interfaces USB Ethernet ports UART and USART Debug port High Speed Multi-Card Interface LCD and touch screen support CAN I2C SPI JTAG WI-FI + BT Module External Watch Dog Hardware Software interface Hardware Configuration Interrupt & I/O Table Booting Sequence First Level Boot Pin assignment Mechanical considerations SMARC connector SPARK-501 HW user manual 1.1

3 Document Revision History Revision Date Description Initial version Add details about V2 fast Ethernet change. 3 SPARK-501 HW user manual 1.1

4 1 Scope The purpose of this document is to provide a guide for integrating the Spark-501 into the target hardware in an easy and fast way so that the use of SoM will shorten and simplify the development process. In order to simplify the integration process we recommend the following process: 1. Read through the integration guide on the required interfaces. 2. Use Shiratech s Pin configuration tool to define the solution For more details if needed please review the SAMA5D3x user manual and for additional questions and support access Shiratech at support@shiratech.com. 1.1 SoM introduction The SPARK-501 is an industrial embedded System-On-Module (SoM) based on Atmel s SAMA5D3x Cortex-A5 system on chip. It offers the optimal balance of the most power efficient Cortex A processor available to date with a high performance CPU running at 528 MHz and a floating point unit. 1.2 SoM models The SOM support two variations of the SAMA5D3x, the D31 for low cost solution and D36 for additional 1GE interface and CAN support. See the table below for the supported interface in each variation: Figure 1 Interface support on the various SAMA5D3 processors 4 SPARK-501 HW user manual 1.1

5 2 SPARK-501 Integration guide The HW integration guide covers all the hardware issues related to the connecting the SoM to the target device starting from power connectivity, connector details, pin-out options, description of the various interfaces and provides reference design for most of the interfaces. By using the same design as the reference board you can shorten the BSP development phase and reduce the option for mistakes. 2.1 Block diagram LDDR2 D[0-31] TX/RX GE PHY RGMII D[0..7] NAND (Optional) TX/RX FE PHY USB 1,2,3 CAN 0,1 MCI 1 SPI 0,1 (2 x CS) I2C 0,1,2 USART 1,2 UART 0,DBUG LCD 18 RGB MII P I N M U X SAM5 D31/D36 SPI 0, CS0 MCI0 D[0..7] I2C0 Serial NOR (Optional) emmc 4-64 GB EEPROM LV DS 18 Dig. Audio GPIO MCI2 D[0..3] USART 3 WI-FI BT Module PWR_En, WKUP, Idle, Sleep PWR Mng. Figure 2 SPARK-501 Block Diagram 2.2 Power connectivity The SPARK-501 uses a single power input, supporting Volts range from which all the other required voltages are taken. The Inlet power should be: Rise time: <= 3ms Input voltage range: V +/- 5% Typical power consumption: 0.5W 5 SPARK-501 HW user manual 1.1

6 S M A R C Vin V PWR_EN Vin -> 3.3 EN Vin -> 1.2 I/O Core/LPDDR2 Ferrit PLL Vin -> 1.8 LPDDR2/IO 1.8 -> 1.2 LDO GE 3.3 -> 2.5 LDO FUSE VBAT Figure 2 SPARK-501internal power scheme The GPIOs of the SAMA5D3x are 3.3V, if 1.8V level is needed it can be done, require a dedicated part number (please approach sales@shiartech.com ) The SPARK-501 support low power modes, it can enter sleep mode by shutting down the main power source leaving only a very small part active for possible wake up interrupt either internal or external. For supporting these modesseveral additional lines are available: VBAT battery input for maintaining the RTC unit and Shutdown Controller within the processor. If not used leave open (will be connected to 3.3V internally). WKUP(Input P128, POWER_BTN#) The POWER_BTN# line is used to wake up the system from a deep sleep mode using an external trigger, if unused should be left open.an internal pull up is assembled on the SOM. The SAMA5D3 have several sleep modes the most power efficient is backup mode, waking up from that mode is via the WKUP pin of the processor only. The POWER_BTN# input on the SMARC connector is also connected to the SAMA5D3 PE15 input, this input can trigger a wake-up of system from ultra-low power mode. Thus the designer can select the required mode to be used. SHDN (Output S154 connector) This pin enable the SW to shut down the power after entering the SW and processor to sleep mode. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system. 6 SPARK-501 HW user manual 1.1

7 Level 1 (3.3V) = Enable, Level 0 (0V) = Shutdown. Note: If this pin is used along with a battery connected to the VBAT signal then the signal should be pulled up to VBAT and not to regular 3.3V. In that way the signal remain valid even when the main power is down. VBAT Atmel SAMA5D WKUP PE15 SHDN SMARC 5V->3.3V 5V S147 VBAT P128 WakeUp S154 Shutdown Figure 3 SPARK-501RTC Backup Power scheme ADVREF - this pin is a reference voltage pin for A/D GPIOs and for resistive touch support, it is set internally to 3.3V. 2.3 Reset The SPARK-501 integrates an internal POR. The NRESET signal is an open-drain interface. It monitors the power and drives the internal and external reset with a default length. After power up this length can be change for the next POR as long as there is a battery backup support. The generated reset signal is used for reset the chips on the module. It also can be used as an input to Push-Button 1.8/3.3 V NRESET S M A R C SAMA5D NRESET Figure 4 SPARK-501 reset scheme an external reset source like a push-button. 7 SPARK-501 HW user manual 1.1

8 2.4 Spark-501 System Cortex-A5 Processor The SPARK-501 uses Atmel's SAMA5D3x ARM Cortex-A5 based CPU as the modules controller. The SAMA5D3x is a family of CPU which implement the ARMv7 architecture and run 32 bits instructions. It includes an FPU (Not NEON) which is tightly integrated into the processor pipeline. The SAM5D3x support different flavors e.g. Single/dual Ethernet, enhanced graphic accelerator, LCD and more. All those flavors are footprint compatible and can be supported by the AT-501 module. The SAM5D3x main features are: 536 MHZ core frequency 32 Kbytes data and instruction cache Fully integrated MMU. Fully integrated FPU (VFPv4) System running at 166 MHz Integrated RTC, POR and WDT Low power mode Multiplex peripherals bus 324 pins BGA package The Spark-501 supports two variations of the SAMA5D3x the SAMA5D31 and SAMA5D Memories The SPARK-501 includes varieties of memory options to support booting, program execution, data storage and ID. The following figure describes the memories mapping of the SPARK-501. LPDDR2 NAND 32 bits Data bus. 512Mbytes memory device. 166 MHz system clock. Uses for SW execution. 8 bits data bus. 256Mbytes up to 1Gbyte(ordering option), or none in case emmc only is used Uses for boot and data storage. 8 SPARK-501 HW user manual 1.1

9 D[0 31] LPDDR 2 D[0-7] NAND MCI 0 emmc SPI 0 CS0 NOR Data Flash SPI 0 CS1 NOR Data Flash MCI 1 SD Card I2C0 EEEPROM Carrier SAM-A5 SOM Figure 5 SPARK-501 Memory scheme NOR Flash (on board ordering option) The Spark-501 can have an internal NOR flash for boot located on SPI0 (using CS0) 1 bits data bus. 256Mbits memory space. NOR Flash External(on carrier board) 1 bits data bus. 256Mbits memory space. Uses for boot. SPI0 CS1 Connected to I2C0 emmc Uses the SAMA5D3's MCI0 interface. Implements 8 data bits. Up to 25 MHz clock. Can be used for Boot and data storage. EEPROM Atmel AT24C01. Uses for ID storage. 9 SPARK-501 HW user manual 1.1

10 Can be used as MAC address for the GE interface. SD External Uses the SAMA5's MCI1 interface. Implements 4 data bits. Up to 25 MHz clock. Can be used for data storage (Not for BOOT). 2.5 Interfaces The SPARK-501 offers a large variety of interfaces over the SMARC connector. The following paragraphs describe the available interfaces along with guidance on how to connect and to use them. For more information, review the SAMA5D3 data sheet USB The SAMA5D3 support 3 USB ports: Port-A support USB 2.0 Host/Device OTG interface. o This port can be programmed as Host or Device. o It can also be programmed as an OTG interface. o By monitoring the VUSB signal it can determine if it is connected to a Host or a device. o This port should be used for connecting by the Atmel SAM-BA tool. Note: For automatic detecting of the external device connected it is recommended to use the ID pin of the USB interface and to connect it to a GPIO of the processor. Port-B supports USB 2.0 Hostinterface. Port-C supports USB 2.0 Host interface. 3.3V 5V Atmel SAMA5D I/O EN/OC# EN USB PWR Switch (Active High) OC# 5V USB Figure 6 SPARK-501 USB connectivity The SAMA5D3 integrates the USB PHY so there is no need for external devices. The module supports power control signals for each of the USB interfaces according to the SMARC standard. To be compatible with the SPARK-501 SW the following I/O need to be connected when using the USB interfaces: PD25 power drives enable and current Over-Flow for port A. PD26 power drives enable and current Over-Flow for port B. PD27 power drives enable and current Over-Flow for port C. PC20 power sense from port A. 10 SPARK-501 HW user manual 1.1

11 PD31 port A ID. Note The EN/OC# control signal are directly connected to the SAMA5 IO interfaces. It includes a pullup on each control signal. The user should program the IO interface to support the EN/OC# feature. The USB ports can be extended to support additional USB ports, using an external USB hub Ethernet ports The SPARK-501 support 1000/100/10 Ethernet port and one 100/10 Ethernet port depending on the type of processor assembled. Ethernet 0 RGMII 4 x TX 125 Mhz 4 x RX Controls Int. NReset Micrel ksz9031 LEDS GE Analog LEDS RJ45 MAG 25M SMARC 25M Ethernet 1 SAM-A5 RMII 2 x TX 50 MHz 2 x RX Control Micrel ksz8081 LEDS FE Analog LEDS RJ45 MAG Figure 7 - Giga Ethernet & Fast Ethernet Interfaces (V1 only - do not use for new designs) 11 SPARK-501 HW user manual 1.1

12 Figure 7 - V2 Giga Ethernet & Fast Ethernet Interfaces Giga Ethernet port (D36 only) The SPARK-501 includes a build in 1GE interface (including physical layer chip)for the D36 assembly option. The Giga Ethernet uses an RGMII interface to interconnect to the processor Ethernet port 0, running at 125 MHz. The 125 MHz clock is generated by the Micrel KSZ9031 Giga Ethernet PHY. Figure 5 describes the Giga Ethernet interface. The Giga Ethernet PHY analog signals (TX+/-, RX+/-) are connected the SMARC edge connector. Two led signal from the GE PHY are also connected to the SOM edge connector. On the carrier board only the magnetic and connector should be placed. The Giga Ethernet signal pairs should be routed from the PHY to the magnetic as differential pairs using 100 ohm impedance. The Physical layer chip is connected via MDC/MDIO interface using the default PHY address is 0001 for both interfaces. For the GE port the following signals are used as well: Interrupt PD-19 of the SAMA5 uses as an interrupt input for the Giga Ethernet PHY. LEDs- Two led signals from the GE PHY are also connected to the SOM edge connector. LED1 - Blinking Activity. LED2 -Link, on when there is link. The leds are connected to the GE PHY through a 470 ohm serial resistor. Note: In case of the SAMA5D31, the pins used for GE should be left unconnected. 12 SPARK-501 HW user manual 1.1

13 Figure 8 - Giga Ethernet schematics /100 Ethernet port The Fast Ethernet interface is available for both the D36, D31.The Fast Ethernet PHY is connected to the SAMA5D3x Ethernet port 1. It uses an RMII interface running at 50 MHz. Note: The Ethernet phy device was changed in version 2 of the Spark-501 from Micrel kzx8081 to LAN8472 which central tap power. PB-12 of the SAMA5 uses as an interrupt input for the Fast Ethernet PHY. The Fast Ethernet PHY analog signals (TX+/-, RX+/-) are connected the SMARC edge connector. Two led signal from the FE PHY are also connected to the SOM edge connector. LED1 - Blinking Activity. LED2 - Link, on when there is link. The Leds are connected to the GE PHY through a 470 ohm serial resistor UART and USART The SAMA5D3 offers 4 USARTs and 2 UARTs and a debug port (Tx, Rx). The ports are available as follows: USART ports The USART ports main features are: 13 SPARK-501 HW user manual 1.1

14 Programmable Baud Rate Generator 5-bit to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications o 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode o Parity Generation and Error Detection o By-8 or by-16 Over-sampling Receiver Frequency o Optional Hardware Handshaking RTS-CTS RS485 with Driver Control Signal IrDA Modulation and Demodulation The USART ports are available as follows: USART0 - Connected to SER1 of the SMARC interface, if SCK is needed as well is available on P31 (if SPI0-CS1 is not used). USART1 - Connected to SER0 of the SMARC interface, if SCK is needed as well is available on P108. USART2 - Connected to SER2 of the SMARC interface, if SCK is needed as well is available on P119. USART3 - Used internally for connecting the Wi-Fi/BLE module. Note: the USART can be configured as SPI interface if required. Figure 9 UART RS232 interface schematics UART ports The UART ports are not available on the serial ports of the SMARC, since the SMARC define only 4 serial interfaces. In case the developer needs additional UART ports, they are available at UART0 on the CAN 0 interface (P143 and P144) in case CAN is not used. UART1 available on AFB lines (S22 an S23). The UART port main features are: Two-pin UART Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator 14 SPARK-501 HW user manual 1.1

15 Even, Odd, Mark or Space Parity Generation Parity, Framing and Overrun Error Detection Automatic Echo, Local Loopback and Remote Loopback Channel Modes Interrupt Generation Debug port The processor has an additional dedicated UART port for debug and controlconnected to the internal debug controller. The Debug port is connected to SER3 offering Tx and RX only interface High Speed Multi-Card Interface The SAMA5D supports up to 3 HSMCI interfaces. MCI0 is used for the internal emmc device and is not available on the SMARC interface. MCI2 is used for connecting the internal Wi-Fi/BLE module and is not available on the edge connector. MCI1 is available on the SMARC interface on the SDIO port (P33-P37, P39-P42), offering 4 data bits. In case an SD is connected to that interface PD30 will be used as a power enable for the card. Note MCI1 cannot be used for boot due to errata on the SAMA5D LCD and touch screen support The SAMA5D3 support an internal LCD controller with build in support for resistive and capacitive touch screen LCD support The SPARK-501 supports two LCD connections: RGB, 18 colors bits parallel bus and control signals. LVDS, 3 lanes and clock differential signals supporting 18 color bits (Ordering option) Atmel SAMA5D PA[12..17] PA[6..11] PA[0..5] Ctrl SN75LVDS83BD RGB to LVDS LCD[18..23] LCD[10..15] LCD[2..7] LVDS0 LVDS1 LVDS2 CLK Figure 10 LCD connectivity options Note The SAMA5 LCD signals are mapped to the SMARC MSB bits e.g. PA[0..5] are connected to LCD[2..7]. For 24 bits display connected the LSB of each color to GND Resistive Touch screen The SAMA5D3 has an ADC controller, which includes a Resistive Touchscreen Controller. It supports 4- wire and 5-wire technologies with the following support: Position and Pressure Measurement for 4-wire screens 15 SPARK-501 HW user manual 1.1

16 Position Measurement for 5-wire screens Average of up to 8 measures for noise filtering Figure 11 Touch screen connectivity example Note: if these pins are not used, they are set to inputs with internal pull up Capacitive Touch screen Supporting capacitive touch screen is available by using the LCD_I2C interface (SMARC connector) CAN The SPARK-501 supports up to two CAN interfaces depending on the processor type. The CAN interfaces are available under the following constrains: CAN 0 Is not available on the standard CAN interface of the SMARC due to limitations in the processor multiplexing however if the SPI 0 CS1 is not used the CAN interface can be used. CAN 1 Is connected to CAN1 interface of the SMARC (P145-P146) I2C There are up to three I2C interfaces available on the SAMA5D3. All three interfaces are available on the edge connector. The availability of the I2C interfaces is dependent on the I/O configuration. The I2C interface requires pull ups on both lines, the pull ups should be placed on the carrier board. The I2C main features are: One, Two or Three Bytes for Slave Address Sequential Read-write Operations Master, Multi-master and Slave Mode Operation Bit Rate: Up to 400 Kbits General Call Supported in Slave mode MBUS Quick Command Supported in Master Mode Connection to DMA Controller (DMA) Channel Capabilities Optimizes Data Transfers The I2C ports are available under the following conditions: I2C 0 Available on the power management I2C interface (P121-P122). If used UART 1 is not available. I2C 1 - Available on the LCD I2C interface (S48-S49) only if SPI 1 CS 1 and 2 are not used. 16 SPARK-501 HW user manual 1.1

17 I2C 2 Available on the General Purpose I2Cinterface (S48-S49) SPI There are up to two SPI interfaces on the SAMA5D3x supporting the following: Programmable as Master or Slave. Up to 25 MHz clock. Up to 4 chips select signal that can be configure as discreet or as a 4 bits logical combination. It is recommended to put a serial resistor on the clock signal close the SOM connector. No need to put pull-up resistors on the data signals. SPI0 can be used for NOR flash boot, CS0 is used for connect on board NOR flash and CS1 for an external NOR flash JTAG The SPARK-501 has a JTAG interface that can be used either for JTAG testing or for connecting an ICE. The selection between the two modes is done using setting JTAGSEL pin 9 of the JTAG connector. JTAGSEL is used for selecting the right mode, for normal mode or ICE open, 1 for JTAG test. Figure 12 JTAG emulator interface 2.6 WI-FI + BT Module The SPARK-501 integrates a WI-FI and BT module. The module is Atmel's ATWILC3000-MR110PA. It is connected to the SAMA5 using the following interfaces: SDIO2 for WI-FI data flow. USART3 for BT data flow. The following signals are the module control signals: PE11 - WI-FI and BT enable. PE12 - WI-FI and BT reset. PE13 - WI-FI and BT interrupt. 17 SPARK-501 HW user manual 1.1

18 2.7 External Watch Dog The SPARK-501 integrates a watch-dog chip (Ordering option). The chip enables resting external devices (SMARC standard requirements). The chip is ST's STWD100. The following signals are used by the watchdog: PA21 Watch-Dog enable. PA20 Watch-Dog input signal. PE0 Watch-Dog output signal. 3 Hardware Software interface 3.1 Hardware Configuration During power up some I/O bits status is latch to configure the CPU. The following table describes the bits and their functionality. Signal Description Default BMS 1 Booting from internal ROM Fixed to 1 internally (SOM) ETH0 Address ETH1 Address The access address to the Ethernet 0 PHY The access address to the Ethernet 1 PHY Table 1 HW Configured After Reset Interrupt & I/O Table The following table describes the SPARK-501I/O configuration used by the SW. To keep compatibility with the SPARK-501SW these I/O must be used for the following interfaces: Signal I/O Description Remarks E0 INTR PD-19 Giga Ethernet 0 interrupt Active Low E1 INTR PB-12 Fast Ethernet 1 interrupt Active Low MCI0 PWR EN PB-10 emmc Power enable 0 PWR Disable 1 PWR Enable MCI1 CD PD-28 SD card detect 0 Card in 1 No card VBUS Sense PC-20 USB port A power sense 0 No power sensed 1 Power sensed 18 SPARK-501 HW user manual 1.1

19 EN5VA/OC# PD-25 USB port A power enable/over current EN5VB/OC# PD-26 USB port B power enable/over current EN5VC/OC# PD-27 USB port C power enable/over current 0 Disable 1 Enable (Default) 0 Disable 1 Enable (Default) 0 Disable 1 Enable (Default) WTD EN# PA-21 Watch Dog enable 0 Enable 1 Disable WTD IN PA-20 Watch Dog trigger Stat change WTD OUT# PE0 Watch Dog Output Active Low Table 2 Configured I/O and Interrupts NOTE More interrupts are available through the SAMA5D I/O pins and can be configured according to the user application. NOTE When an interface is not in use its relevant I/O can be used as a general purpose I/O. 3.3 Booting Sequence The SPARK-501has 3 boot phases: First level boot loader running from internal ROM. Device configuration running from internal RAM. SW downloads from NVRAM (emmc, NAND or NOR) to DDR2 and execution First Level Boot After POR the SAMA5D runs the "First Level Boot loader" program stored in its internal ROM. The program configures the SAMA5D clocks and looks for executable program in one of the non-volatile memories (See SAMA5D3x datasheet for more details). The optional memories are: NAND (SOM) emmc (SOM) Serial NOR (SOM). Serial NOR (Carrier) The following figure describes the optional boot memories and its priorities. 19 SPARK-501 HW user manual 1.1

20 VCC BMS = 1 D [0-7] NAND BSEL2 = 1 MMC 0 SPI 0/CS0 emmc NOR Data Flash SPI 0/CS1 NOR Data Flash BSEL2 = 0 SAM-A5 SAM BA DBUG Port A SMARC Carrier SOM USB <-> RS-232 Figure 13- Boot Sequancing Priority USB (A/B) USB (A/B) Note BSEL2 (SMARC standard) enable booting from the SOM or the Carrier board. BSEL2 disable all access to the NV memories on the SOM if disabled. If the "First Level Boot-Loader" doesn't find an executable program in one of the non-volatile memories, it configures the Debug port (RS-232) and the USB port (Port A as device) to wait for external program download from the PC. For more information see the Atmel's boot sequencing chapter in the SAMA5D datasheet. Note There is no option to run the first level boot from a usd card. 3.4 Pin assignment For pin assignment, review the Spark-501 pinout configuration tool. 20 SPARK-501 HW user manual 1.1

21 3.5 Mechanical considerations The height of devices in the PS is up to 1mm. The mechanical dimensions are according to the SMARC standard, the full details are available at The following figures are taken from the standard to show the physical dimensions of the module and the required layout of the carrier board. Note that the Spark is using the smaller option of 82x50. The maximum height of devices on the PS(print size) is 1mm. 21 SPARK-501 HW user manual 1.1

22 3.5.1 SMARC connector The SMARC connector is available from several vendors, below are the part list from Foxconn, other part numbers from other vendors are available in the SMARC HW specification. Vendor Vendor P/N Stack Height Body Height Contact Plating Foxconn AS0B821-S43B - *H 1.5mm 4.3mm Flash Black Foxconn AS0B821-S43N - *H 1.5mm 4.3mm Flash Ivory Foxconn AS0B826-S43B - *H 1.5mm 4.3mm 10 u-in Black Foxconn AS0B826-S43N - *H 1.5mm 4.3mm 10 u-in Ivory Foxconn AS0B821-S55B - *H 2.7mm 5.5mm Flash Black 22 SPARK-501 HW user manual 1.1

23 Foxconn AS0B821-S55N - *H 2.7mm 5.5mm Flash Ivory Foxconn AS0B826-S55B - *H 2.7mm 5.5mm 10 u-in Black Foxconn AS0B826-S55N - *H 2.7mm 5.5mm 10 u-in Ivory Foxconn AS0B821-S78B - *H 5.0mm 7.8mm Flash Black Foxconn AS0B821-S78N - *H 5.0mm 7.8mm Flash Ivory Foxconn AS0B826-S78B - *H 5.0mm 7.8mm 10 u-in Black Foxconn AS0B826-S78N - *H 5.0mm 7.8mm 10 u-in Ivory 23 SPARK-501 HW user manual 1.1