Gamma-ray Large Area Space Telescope (GLAST) Large Area Telescope (LAT) Integration and Test Subsystem Electrical Performance Tests

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1 GLAST LAT Document Title LAT I&T Electrical Performance Tests Document # Date Page 1 of 24 LAT-MD March 11, 2003 Author(s): L. Wai Subsystem/Office Integration and Test Subsystem Approval(s) E. Bloom J. Clinton G. Haller D. Marsh Gamma-ray Large Area Space Telescope (GLAST) Large Area Telescope (LAT) Integration and Test Subsystem Electrical Performance Tests

2 LAT-MD LAT I&T Electrical Performance Tests Page 2 of 24 Change History Log Revision Effective Date Description of Changes 1 March 11, 2003 Initial Release

3 LAT-MD LAT I&T Electrical Performance Tests Page 3 of 24 Contents 1. PURPOSE SCOPE ACRONYMS / DEFINITIONS Acronyms Definitions APPLICABLE DOCUMENTS OVERVIEW Acceptance Data Packages Integration Facility Test Beds I&T Electrical Test Flow REQUIRED COMPONENTS Electronics Subsystem Contribution Power Supplies TEM-Level Test Equipment GASU-Level Test Equipment Mechanical Hardware Embedded System Software I&T Subsystem Contribution I&T Subsystem Online Contribution SPECTRUM-ASTRO Contribution Tracker Subsystem Contribution Tracker Test Scripts Calorimeter Subsystem Contribution Calorimeter Test Scripts ACD Subsystem Contribution ACD Test Scripts ACCEPTANCE TESTS Tracker Module Acceptance Testing Tracker Acceptance Test Sequence Tracker Acceptance Test Data Calorimeter Module Acceptance Testing Calorimeter Acceptance Test Sequence Calorimeter Acceptance Test Data ACD Acceptance Testing ACD Acceptance Test Sequence...13

4 LAT-MD LAT I&T Electrical Performance Tests Page 4 of ACD Acceptance Test Data Flight Electronics Acceptance Testing Flight Electronics Acceptance Test Sequence Flight Electronics Acceptance Test Data LAT ASSEMBLY TESTS Per-Bay Functional Test Per-Bay Test Sequence Per-Bay Test Data Multi-Tower Functional Test Multi-Tower Test Sequence Multi-Tower Test Data INtegrated ACD System Level Test Integrated ACD System Level Test Sequence Integrated ACD System Level Test Data Comprehensive Performance Reference Test Comprehensive Performance Reference Test sequence Comprehensive Performance Reference Test Data POST-ASSEMBLY TESTS Comprehensive Performance Test Comprehensive Performance Test Sequence Comprehensive Performance Test Data Limited Performance Test Limited Performance Test Sequence Limited Performance Test Data Aliveness Test Aliveness Test Sequence Aliveness Test Data I&T REDUNDANT PATH TESTS APPENDIX: ETHERNET PORT ASSIGNMENTS... 24

5 LAT-MD LAT I&T Electrical Performance Tests Page 5 of PURPOSE This note defines the LAT I&T Electrical Performance Tests which will be used to validate the functionality of the LAT instrument during Integration and Test at SLAC-Bldg.33 and NRL. 2. SCOPE This document covers the activities that occur at SLAC and NRL using components provided by other subsystems as well as components provided by the Integration and Test Subsystem. This document clarifies the configuration and the test methodologies of each of the electrical test beds, and hardware/software provisional responsibility/schedule. The document is divided into sections defining the acceptance testing of flight hardware deliverables to I&T, testing during assembly of the LAT, and testing during environmental testing and spacecraft integration. The required components are described in Section 6 along with which organization will provide the components. The acceptance tests are described in Section 7, testing during LAT assembly are described in Section 8, and post-assembly testing are described in section ACRONYMS / DEFINITIONS 3.1. ACRONYMS ACD ASIC CAL CDE DAQ EGSE EMI EPU GLAST GLT GTE GUI HPK I&T LAT MCM MGSE PIN Anticoincidence Detector Application Specific Integrated Circuit Calorimeter Crystal Detector Element Data Acquisition System Electrical Ground Support Equipment Electromagnetic Interference Event Processor Unit Gamma-ray Large Area Space Telescope Global Trigger Global Trigger Electronics Graphical User Interface Hamamatsu Photonics K (Japan) Integration and Test Large Area Telescope Multi Chip Module for Tracker Mechanical Ground Support Equipment Positive-Intrinsic-Negative, a type of semiconductor

6 LAT-MD LAT I&T Electrical Performance Tests Page 6 of 24 TEM-PSU Tower Electronics Module Power Supply Unit SSD Silicon Strip Detector SVAC Science Verification Analysis and Calibration TEM Tower Electronics Module TBD To Be Determined TKR Tracker 3.2. DEFINITIONS TEM-level Per-bay system, includes integrated TKR, CAL, TEM, TEM-PSU GASU-level Can include any subset of entire LAT system 4. APPLICABLE DOCUMENTS Documents relevant to the Engineering Model System Level Test Plan. LAT-PS LAT Assembly Sequence LAT-MD LAT I&T Acceptance Data Package (I&T ADP) LAT-MD LAT I&T SVAC Plan

7 LAT-MD LAT I&T Electrical Performance Tests Page 7 of OVERVIEW 5.1. ACCEPTANCE DATA PACKAGES Subsystem-level electrical performance tests will be performed to collect data for LAT I&T Acceptance Data Packages (LAT-MD-01555). Upon completion of this step, flight hardware is ready for formal hand-off to LAT I&T for assembly into LAT INTEGRATION FACILITY TEST BEDS The location of electrical test beds for subsystems in the LAT Integration Facility (Building 33, SLAC) are shown in the following diagram. The assignment of ethernet ports are given in the appendix, section 11. A ELX B ROOM 101 ROOM 103 D C C,D ROOM 102 I&T ACD B A E F TKR G A CAL H ROOM 104 I&T VDG Unit Electrical test beds will be used for electrical testing of subsystem components prior to integration to LAT (either for Acceptance Data Package and/or post-ship to SLAC from off-site suppliers). Flight hardware, MGSE, and test stands are grounded and resistance of ground connections are verified by measurement. ESD control procedures are found in LAT-MD The Electrical Integration Coordinator will check flight cables for proper grounding, resistance, and continuity. Once safe-tomate tests are completed, the Electrical Integration Coordinator will mate flight cables and update the Flight Mate Log using the I&T Flight Hardware Database. As LAT is assembled, flight hardware will undergo intermediate system level functional tests. Online Workstations will be located in the Control room, room 102, and the LAT Integration room, room 104. Online Workstations will communicate with the EGSE test stands in room 104, where flight hardware will be located during assembly of LAT. Visual and phone contact will be possible through the intervening wall between rooms 102 and 104. The Electrical Performance Test Manager will perform tests from either the Control room or the Integration room and validate the test reports. The validated hardcopy test reports will be transferred to the LAT I&T Traveler as soon as possible after the tests are completed.

8 LAT-MD LAT I&T Electrical Performance Tests Page 8 of I&T ELECTRICAL TEST FLOW The I&T electrical test flow for flight hardware can be summarized as follows: a) Subsystem flight hardware stand-alone acceptance testing (section 7) b) LAT assembly tests (section 8) c) Post-assembly tests (section 9) In section 10 we define the I&T tests for redundant electrical paths.

9 LAT-MD LAT I&T Electrical Performance Tests Page 9 of REQUIRED COMPONENTS This section describes the required components and is organized by the subsystem who will contribute the items ELECTRONICS SUBSYSTEM CONTRIBUTION The Electronics Subsystem will provide the following electrical test equipment: Power Supplies Three types of test stands will be used for I&T electrical performance tests of flight hardware: TEM- Level, GASU-Level, and Spacecraft Interface Simulator (SIS). For each test stand, a power converter will be built to transform from 120W A/C building power source to 28W D/C LAT power source. The total power of the LAT is limited to 650W, therefore the GASU-Level test stand and SIS will require 5.5A from 120W A/C building power source. Details of power supplies are TBD TEM-Level Test Equipment Three complete sets of TEM-level Test Equipment are required, one for LAT assembly, one for parallel TKR Flight Hardware acceptance testing, and one for parallel CAL flight hardware acceptance testing. Electronics hardware for the TEM-Level Test Equipment is supplied by the Electronics Subsystem. The components are: VME crate MVME2306 Single Board Computer Transition board including Global Trigger. LAT COMM boards or LAT Communications Board (LCB) Choice depends on maturity of LCB 2 Tower Electronics Modules (TEM) v2 Connectors loaded to support full EM test (CAL, TKR). Connectors loaded to support TKR EM test. Power Supply Assembly (PSA) 28 V Spacecraft Battery Cables and connectors to interconnect the above except for the TKR to TEM and CAL to TEM cables that are supplied by the TKR and CAL subsystems respectively GASU-Level Test Equipment Three complete sets of GASU-Level Test Equipment are required, one for LAT assembly, one for parallel ELX Flight Hardware receiving into the I&T Subsystem, and one for parallel ACD acceptance testing.

10 LAT-MD LAT I&T Electrical Performance Tests Page 10 of 24 Parts are TBD Mechanical Hardware The Electronics Subsystem will be supplying an aluminum Tower Electronics Module (TEM) Box and an aluminum Power Supply Unit (TEM-PSU) Embedded System Software Electronics will supply the following embedded system software: Hardware drivers (Gives access to hardware registers) Command Server (Turns commands into driver subroutine calls) Event Data Server (Sends event data downstream) Monitoring Data (housekeeping) Server A Command Server, Event Data Server, and the Monitoring Data Server will be provided by I&T online if the FSW does not have these items ready I&T SUBSYSTEM CONTRIBUTION I&T Subsystem Online Contribution The Online contribution to the TEM-level and GASU-level test equipment consists of the following: Workstation The Online department within the I&T Subsystem will provide the workstation and the workstation software. The software will have the following functionality. Command Client (Gives scripts, etc. access to embedded system) Event Client (Receives event data) Message log (Informational, alerts, etc.) Event data logging Run Control and GUI Command/Monitoring GUI Electronic Log book Core scripts Subsystem scripts System scripts Visualizations The EGSE will contain HippoDraw visualization software, and event displays written in Qt. The visualization software is provided by the Online department within the I&T Subsystem.

11 LAT-MD LAT I&T Electrical Performance Tests Page 11 of 24 TBD Aux Trigger Plans 6.3. SPECTRUM-ASTRO CONTRIBUTION Spacecraft Interface Simulator, parts TBD 6.4. TRACKER SUBSYSTEM CONTRIBUTION Tracker Test Scripts The tracker subsystem will provide the necessary test scripts for standalone functional testing and operation CALORIMETER SUBSYSTEM CONTRIBUTION Calorimeter Test Scripts The Calorimeter Subsystem will provide the necessary test scripts for standalone functional testing and operation ACD SUBSYSTEM CONTRIBUTION ACD Test Scripts The ACD Subsystem will provide the necessary test scripts for standalone functional testing and operation.

12 LAT-MD LAT I&T Electrical Performance Tests Page 12 of ACCEPTANCE TESTS This section defines the Acceptance Test Process. Acceptance tests will be performed to collect data for I&T Acceptance Data Packages. In addition, if subsystem flight hardware is delivered to SLAC, then the acceptance tests will be performed at SLAC subsequent to delivery and prior to integration to LAT. This section is broken into four major sections, one for each electrical subsystem: TKR, CAL, ACD, and ELX TRACKER MODULE ACCEPTANCE TESTING Tracker Acceptance Test Sequence The tracker acceptance test sequence is summarized as follows: a) Basic tests of tracker related TEM registers and read back tracker environmental quantities. b) Lower the thresholds and strobe each electronics channel to check for dead channels. Dead channel list will be derived. c) Set nominal thresholds and perform charge injection scans for each channel. The derived electron noise at amplifier input and gain will be used to determine if individual electronics channels are in non-conformance with pre-defined limits Tracker Acceptance Test Data Test data to be collected are summarized in the following table: Data TKR Single-hit MIP efficiency SVAC ID C9 Charge Injection TKR Noisy Channels C10 TKR Dead Channels C11 TKR Threshold Scan TKR TOT Signal C12 TKR High Rate Test Muon Scan Test Method Radioactive Source TKR Dead time TKR Redundant Paths Van de Graaff S/C Interface Simulator Pre-defined functional test sequences will be executed by Run Control and test reports will be automatically generated at the end of functional test sequences. Test reports will be entered into the electrical performance test traveler and summarize the test data and determine success based upon pre-defined pass/fail criteria TBD.

13 LAT-MD LAT I&T Electrical Performance Tests Page 13 of CALORIMETER MODULE ACCEPTANCE TESTING Calorimeter Acceptance Test Sequence The calorimeter acceptance test sequence is summarized as follows: a) Basic tests of calorimeter related TEM registers and read back calorimeter environmental quantities. b) Then we raise the gain and strobe each electronics channel to check for dead channels. Dead channel list will be derived. c) Set nominal pedestals/gains and perform charge injection scans for each channel. The derived pedestals and gains will be used to determine if individual electronics channels are in nonconformance with pre-defined limits Calorimeter Acceptance Test Data Test data to be collected are summarized in the following table: Data SVAC ID Charge Injection Muon Scan CAL Light Yield C16 CAL Pedestals C18 CAL Electronic Gain C19 CAL Integral non-linearity C20 CAL Noisy Channels C22 CAL Dead Channels C23 CAL LO Discriminator C24 CAL HI Discriminator C25 CAL Zero-Suppress Thresh. C26 Test Method Radioactive Source CAL High Rate Trigger CAL Redundant Paths Van de Graaff S/C Interface Simulator Pre-defined functional test sequences will be executed by Run Control and test reports will be automatically generated at the end of functional test sequences. Test reports will be entered into the electrical performance test traveler and summarize the test data and determine success based upon pre-defined pass/fail criteria TBD ACD ACCEPTANCE TESTING ACD Acceptance Test Sequence The ACD acceptance test sequence is summarized as follows: a) Basic tests of AEM registers and read back ACD environmental quantities.

14 LAT-MD LAT I&T Electrical Performance Tests Page 14 of 24 b) Lower the thresholds and strobe each electronics channel to check for dead channels. Dead channel list will be derived. c) Set nominal thresholds and perform charge injection scans for each channel. The derived electron noise at amplifier input and gain will be used to determine if individual electronics channels are in non-conformance with pre-defined limits ACD Acceptance Test Data Test data to be collected are summarized in the following table: Data SVAC ID Charge Injection Muon Scan ACD Detection Efficiency C1 ACD Veto threshold C2 ACD High Threshold C3 ACD Pedestals C4 ACD Electronic Gain and Linearity ACD High Rate Trigger ACD Redundant Paths C5 Test Method Radioactive Source Van de Graaff S/C Interface Simulator Pre-defined functional test sequences will be executed by Run Control and test reports will be automatically generated at the end of functional test sequences. Test reports will be entered into the electrical performance test traveler and summarize the test data and determine success based upon pre-defined pass/fail criteria TBD FLIGHT ELECTRONICS ACCEPTANCE TESTING Flight Electronics Acceptance Test Sequence TBD Flight Electronics Acceptance Test Data TBD

15 LAT-MD LAT I&T Electrical Performance Tests Page 15 of LAT ASSEMBLY TESTS This section defines the tests during LAT assembly. It is broken into four major sections: per-bay functional test, multi-tower functional test, Integrated ACD System Level Test, and comprehensive reference performance test PER-BAY FUNCTIONAL TEST Per-Bay Test Sequence The per-bay functional test sequence is summarized as follows: Tracker a) Repeat tests as per tracker acceptance test sequence above Calorimeter b) Repeat tests as per calorimeter acceptance test sequence above Tracker-Calorimeter system level c) Trigger on the calorimeter to check the relative efficiency of the 3-in-a-row trigger. d) Trigger on the tracker, perform online muon reconstruction, and check for synchronization and integrity of the calorimeter data. e) Muon scan will be performed on each crystal. The derived crystal response and attenuation will be used to determine if individual crystals are in non-conformance with pre-defined limits. High Rate Test f) High rate Van de Graff exposure will push system to orbital trigger rates to verify no loss of data and/or data quality Per-Bay Test Data All test data described in acceptance testing for TKR and CAL will be collected for per-bay functional test. In addition, test data to be collected are summarized in the following table: Data SVAC ID Charge Injection Muon Scan Test Method Radioactive Source Van de Graaff TKR-CAL High Rate Trigger TKR-CAL Event Synchronization TKR-CAL Redundant Paths S/C Interface Simulator Pre-defined functional test sequences will be executed by Run Control and test reports will be automatically generated at the end of functional test sequences. Test reports will be entered into the electrical performance test traveler and summarize the test data and determine success based upon pre-defined pass/fail criteria TBD.

16 LAT-MD LAT I&T Electrical Performance Tests Page 16 of MULTI-TOWER FUNCTIONAL TEST Multi-Tower Test Sequence The multi-tower functional test sequence is summarized as follows: Per-Bay Tests a) Repeat of per-bay tests defined above using GASU-Level test equipment for each individual bay Tower-to-Tower synchronization b) Trigger on the tracker, perform online muon reconstruction, and check for synchronization of the event data. High Rate Tests c) Expose and trigger on high rate test beam and check for integrity of the event data Multi-Tower Test Data All test data described in per-bay functional test data will be collected for the multi-tower test. In addition, test data to be collected are summarized in the following table: Data Tower-to-Tower synchronization SVAC ID Charge Injection Muon Scan Test Method Radioactive Source Van de Graaff Multi-tower high rate trigger Multi-tower Redundant Paths S/C Interface Simulator Pre-defined functional test sequences will be executed by Run Control and test reports will be automatically generated at the end of functional test sequences. Test reports will be entered into the electrical performance test traveler and summarize the test data and determine success based upon pre-defined pass/fail criteria TBD INTEGRATED ACD SYSTEM LEVEL TEST Integrated ACD System Level Test Sequence The multi-tower functional test sequence is summarized as follows: Multi-Tower Test a) Repeat of multi-tower test defined above using GASU-Level test equipment for all 16 bays ACD Tests b) Repeat of all tests defined in ACD acceptance tests using GASU-Level test equipment c) High rate test beam on ACD ACD-Tower synchronization d) Trigger on the tracker, perform online muon reconstruction, and check for synchronization of the ACD event data.

17 LAT-MD LAT I&T Electrical Performance Tests Page 17 of 24 High Rate Tests e) Expose and trigger on high rate test beam and check for integrity of the event data Integrated ACD System Level Test Data All test data described in acceptance testing for ACD, plus multi-tower test data, will be collected for the integrated ACD system level test data. In addition, test data to be collected are summarized in the following table: Data ACD-Tower synchronization SVAC ID Charge Injection Muon Scan Test Method Radioactive Source Van de Graaff ACD-Tower high rate trigger ACD-Tower Redundant Paths S/C Interface Simulator Pre-defined functional test sequences will be executed by Run Control and test reports will be automatically generated at the end of functional test sequences. Test reports will be entered into the electrical performance test traveler and summarize the test data and determine success based upon pre-defined pass/fail criteria TBD.

18 LAT-MD LAT I&T Electrical Performance Tests Page 18 of COMPREHENSIVE PERFORMANCE REFERENCE TEST Comprehensive Performance Reference Test sequence The LAT I&T Comprehensive Performance Test sequence is summarized in the following table: Test Name Type Power S/C Interface Test Point LPT LAT Initialization Power-Up/Boot 1553 Bus Interface 1553 Bus SC Command Interface LAT Commanding Housekeeping Data Telemetry Science Data Collection Telemetry GPS Timing and GRB Alert Timing LAT CPU-to-CPU Communication FSW Internal LAT Subsystem Configuration FSW Internal LAT Environmental Sensors FSW Internal Front End Strobe FSW Internal Front End Charge Injection Scan FSW Internal TKR Cosmic Ray Trigger I&T CAL Cosmic Ray Trigger I&T High Rate Trigger I&T Event Filtering FSW Internal LAT Pointing Calculation FSW Internal Pointing Request Handling SC Commanding Mode Operations LAT Commanding Subsystem Diagnostics and Calibration FSW Internal Thermal Control System Thermal Control Comprehensive Redundant Paths I&T The individual tests are described in more detail as follows: a) 1553 bus interface. This test shall first verify the electrical characteristics of the LAT 1553 interface, and then demonstrate (in conjunction with a spacecraft simulator) that the LAT can exist on the bus with out responding to messages directed to other remote terminals. Next, processing of telemetry requests shall be demonstrated, followed by exercising the command interface to the LAT and verifying that all commands and command data are correctly interpreted. Commands need not be executed to successfully carry out this test. Timing measurements for the standard message traffic shall also be performed. b) SC command interface. All LAT commands shall be exercised, either through the 1553 interface or via test connection to SIU if 1553 interface is not implemented, and correct response shall be verified in telemetry. This test shall verify the capability to successfully upload data into

19 LAT-MD LAT I&T Electrical Performance Tests Page 19 of 24 a specified block of memory and verify the correct memory contents. This test shall also demonstrate the successful dump of the contents of a specific block of memory. Anomaly conditions including bad commands, bad uploads, and partial loads will also be tested. c) LAT housekeeping and low rate science data collection. This test shall verify the successful collection, sampling rate, formatting, down linking and transformation into user units of housekeeping and low-rate science data. If telemetry content is mode specific, this test shall verify the correct content as a function of mode. If dwell telemetry is implemented, this test shall verify setup and collection of dwell data. d) Wideband telemetry (science data interface to vehicle). This test shall verify the correct formatting of events and associated supporting data, followed by transmission through the external LAT interface in a form that may be correctly decoded. e) GPS Timing and GRB Alert. This test shall verify the timing and processing of the GPS time hack and GRB alert signal from the external interface. An external test detector will measure the timing of muons passing through the LAT in order to validate the accuracy/precision of the GPS time stamp. f) CPU-to-CPU communications (SIU/EPUs). This test shall verify the communications protocol for sending and receiving information between the CPUs, including timing, acknowledgments and other transport level functions. This test may be performed with both the SIU and EPU tasks running on a single processor. This test shall verify that the SIU can configure each EPU as desired via the CPU-to-CPU communications protocol and receive the necessary information back to verify the configuration. This test shall verify the correct transmission, decoding and reply sequence for each configuration message between the SIU and the EPU(s). g) Instrument internal command, configuration, and configuration read back. This test shall verify the ability of the SIU to configure the T&DF, TKR, CAL, and ACD subsystems as desired and read back the necessary configuration information to completely determine the T&DF subsystem configuration. h) Read instrument internal environmental quantities. This test shall verify the ability of the SIU to read back the internal environmental quantities associated with the TKR, CAL, and ACD subsystems. i) Front-end electronics strobe. This test will lower the thresholds on GTFE and GAFE channels, raise the gain on GCFE channels, and strobe each one. This test will check for dead front-end channels, readout controller chips, and flex cable failures. j) Front-end electronics charge injection scan. This test will set nominal thresholds on GTFE and GAFE channels, set nominal gain on GCFE channels, and perform charge injection scans on each one. This test will check for noisy, non-linear, or otherwise non-conforming GTFE, GCFE, and GAFE channels. k) Cosmic ray scan by triggering on tracker only. This test will check for PIN diode or crystal failure; ACD tile or PMT failure; event data loss. l) Cosmic ray scan by triggering on calorimeter only. This test will check for SSD failure; ACD tile or PMT failure; event data loss. m) High rate trigger test. This test will check for loss of event data at orbital particle exposure rates. This can be accomplished with either a high rate Van de Graff exposure or Airborne Cosmic Test.

20 LAT-MD LAT I&T Electrical Performance Tests Page 20 of 24 n) Event filtering. This test shall verify that the on-board filtering algorithms running on the EPU(s) achieve the purity/efficiency ratios predicted by Monte Carlo. The test shall include running a specific set of scenarios derived from Monte Carlo simulations with known expected results. The filtering algorithms must provide acceptable results for each scenario in order to pass this test. This test shall verify the end-to-end processing of a known pattern of data from the LAT electronics to the EPUs. A pre-determined charge signal shall be injected into the electronics at the detector interface and the resulting event data shall be compared to expected values. This test shall include at least 3 scenarios for coverage of various readout paths (to verify redundancy) and readout modes (to verify event data structures). o) FSW and LAT initialization including EEPROM management. This test shall verify that the SIU and EPU(s) can correctly boot themselves, establish a reference state based upon information in nonvolatile storage, and then power and initialize the remaining LAT subsystems in the expected manner, resulting in a known reference state at the end of the process. This state shall be verified through internal configuration read back and LAT telemetry. This test shall verify the mechanisms for recovery should the LAT or one of its processors become nonoperational or lose communications, either internally or with the SC. This test shall include a number of scenarios: orderly shut-down and re-initialization of LAT when communications with SC are lost, re-initialization of the SIU by the watchdog function, re-initialization of one or more EPUs by the SIU or when the EPU watchdog function is triggered. p) LAT pointing calculations. This test shall verify that the SIU FSW can promptly transform pointing vectors reconstructed from event data between the LAT relative coordinate system and the celestial coordinate system. The transformation shall be based on GPS, attitude and orbit information provided by the S/C and the event time tag read in with each event. Using simulated events and simulated SC time/attitude data, the test will demonstrate the accurate reconstruction of the Monte Carlo provided primary particle vector in celestial coordinates. q) GRB handling/repointing requests. This test shall verify that the SIU FSW correctly handles and responds to GRB alerts and repointing requests from both the ground and the GBM (via the SC). Verification shall include a variety of scenarios including repointing enable, different operational modes and conflicting requests. The test shall verify that the SIU FSW responds to these alerts and requests properly, rejecting the appropriate ones and forwarding repointing requests to the SC for the other cases. r) Additional science processing. This test shall verify the SIU FSW capability to monitor for and detect GRBs in the LAT science data. The test shall involve a variety of simulated observing scenarios based on Monte Carlo data with signal concentrations in various portions of the FOV. The test shall verify the detection sensitivity and location accuracy requirements for the LAT. This test shall also verify the SC notification function and timing requirement. This test verifies the LAT s internal logic for requesting repointing for LAT detected GRBs. Verification shall include a variety of scenarios including repointing enable, different operational modes and conflicting requests. The test shall verify that the SIU FSW responds to these events properly, rejecting the appropriate ones and forwarding repointing requests to the SC for the other cases. s) Operational modes. This test shall verify that the SIU FSW can perform the correct transition of the LAT into Safe Mode upon command and subsequent recovery via Engineering Mode. It shall also verify the correct response to SAA entry commands and subsequent recovery. This test shall verify correct transitions between the various science observation modes: Sky Survey

21 LAT-MD LAT I&T Electrical Performance Tests Page 21 of 24 Mode (non-rocking as well as various rocking profiles), Pointed Observation Mode, Repointed Observation Mode and Autonomous Repointing Mode. t) LAT diagnostic and calibration modes. This test shall verify that the SIU FSW properly transitions to Diagnostic and Calibration Mode upon command and then executes the requested diagnostic and calibration algorithms provided by the subsystem teams. u) Thermal Control System (TCS). This test shall verify that the SIU FSW can successfully maintain the LAT within thermal limits via the TCS implementation. This test shall have ambient versions with verification through simulation and a thermal/vacuum version with active control. v) Comprehensive Redundant Path Tests. This test will cycle through all redundant path test series as defined in section 10 below Comprehensive Performance Reference Test Data All test data described in integrated ACD system level test data will be collected for reference comprehensive performance test. In addition, test data to be collected are summarized in the following table: TBD Pre-defined functional test sequences will be executed by Run Control and test reports will be automatically generated at the end of functional test sequences. Test reports will be entered into the electrical performance test traveler and summarize the test data and determine success based upon pre-defined pass/fail criteria TBD.

22 LAT-MD LAT I&T Electrical Performance Tests Page 22 of POST-ASSEMBLY TESTS This section defines the tests after the LAT is assembled. It is broken into three major sections: comprehensive performance test, limited performance test, and aliveness test COMPREHENSIVE PERFORMANCE TEST Comprehensive Performance Test Sequence As per Comprehensive Reference Performance Test Sequence above Comprehensive Performance Test Data As per Comprehensive Reference Performance Test Data above LIMITED PERFORMANCE TEST Limited Performance Test Sequence As per table in section 8.4.1, tests marked under column LPT Limited Performance Test Data TBD 9.3. ALIVENESS TEST Aliveness Test Sequence TBD Aliveness Test Data TBD

23 LAT-MD LAT I&T Electrical Performance Tests Page 23 of I&T REDUNDANT PATH TESTS The basic method for test of redundant paths in I&T is as follows. A large sequence of online schema will be defined which mask out individual or combinations of Front Ends, Readout Controllers, Cable Controllers, TEMs. The tests will consist of looping through the schema and taking test data to validate the redundant electrical paths. The I&T Redundant Path Test series are summarized in the following table: Test Series Unit Redundant Paths # Units Total Fault Tests Combinations 1 Power Distribution Unit 2 2 None, A, B 3 1 PDU-GASU Cable 2 2 None, A, B 3 1 SIU 2 2 None, A, B 3 1 EPU 3 3 None, 1, 2, Total: CAL Cable Controllers 2 64 None, All A, All B 3 2 CAL Readout Controllers None, All A, All B 3 2 CAL Front Ends None, All A, All B 3 2 Total: 27 3 TKR Cable Controllers None, All A, All B 3 3 TKR Readout Controllers None, All A, All B 3 3 TKR Front Ends None, All A, All B 3 3 Total: 27 4 ACD Cable Controllers 2 24 None, All A, All B 3 4 ACD Readout Controllers 2 12 None, All A, All B 3 4 ACD Front Ends None, All A, All B 3 4 Total: 27 All Grand Total: 189

24 LAT-MD LAT I&T Electrical Performance Tests Page 24 of APPENDIX: ETHERNET PORT ASSIGNMENTS Room Panel Port Subnet IP Address Operating System Subsystem 102 A A C B33MON01,,B33MON08 Video Camera Monitoring 102 C B33MON09 Win 2000 Monitoring 102 D B33INT01 Win 2000 I&T 102 D B33INT02 VxWorks I&T 103 A A B 1 B33ELX01 Win 2000 ELX 103 B 2 B33ELX02 VxWorks ELX 103 C C D D E E F B33CAL01 Win 2000 CAL 103 F B33CAL02 VxWorks CAL 103 G 1 Visitor B33TKR01 Win 2000 TKR 103 G B33TKR02 Win 2000 TKR 103 H B33TKR03 Win 2000 TKR 103 H 2 B33TKR04 VxWorks TKR 104 A B33INT03 Win 2000 I&T 104 A B33INT04 VxWorks I&T 104 B B33ACD01 Win 2000 ACD 104 B B33ACD02 VxWorks ACD

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