Altera PCIe reference design testing CRU INDIA TEAM
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1 Altera PCIe reference design testing CRU INDIA TEAM
2 We have found four example designs : Example Design :Variation 1. Stratix V Avalon-ST Interface for PCIe Solutions -- for better understanding of PCIe hip 3. V-Series Avalon-MM DMA Interface for PCIe Solutions high performance DMA engine 2. Stratix V Avalon-MM Interface for PCIe Solutions for quick design 4. PCI Express Multi-Channel DMA Interface--multichannel DMA,support 8chs, one mem for 8 chs
3 PCIe_Testing There are multiple PCIe reference design available in web. We have selected reference design based on 1 st and 3 rd example design: -- Stratix V Avalon-ST Interface for PCIe Solutions -- V-Series Avalon-MM DMA Interface for PCIe Solutions APPs --Both the reference design includes a Windows-based software application that sets up the DMA transfers. The software application also measures and displays the performance achieved for the transfers. --We have another jungo app that detect the presence of Altera board on PCI bus and fetch the details of reference design. Ref design selection: --Reference design1 based on 1 st example design has multiple variation.we have selected the three of them --Gen 1 X8/Gen2 X8/Gen3 X4 --Reference design2 based on 3 rd example design also has multiple variation.we have selected the one of them --Gen 3 X8 There are two computers in VECC,one support upto Gen2X8 and another upto Gen3 X8. We are not able to install the windows application for ref design 1 on computer that support upto Gen3X8. So,the result for DMA is for Gen2 X8 We are able to install the drivers for ref design 2 on computer that support upto Gen3X8.Device manager has listed the Altera board. But, not able to run the application prog. till now.. So, right now we do not have results for DMA of reference design 2.
4 Reference design 1 User design contains the DMA engine Reference design 2 User design contains the only the dual port RAM, DMA is accessed through MM regs
5 Board and system setup Before prog. the FPGA,we have to change some DIP switches setting to create the testing environment and manage the trade off b/n configuration time and bus enumeration time Problem --Configuration time is much much greater than Bus enumeration time --FPGA will be still in configuration mode after bus enumeration, So, host will not detect PCIe based FPGA board Reasons behind solution: --FPGA needs power for configuration. --After configuration FPGA needs Power (either via PCI BUS or externally) to hold the configuration. --But when we shut down and restart or restart the host.,fpga will not get power for some time in case of Power source=pci BUS. --So, FPGA will lose its configuration. --So, We need to apply external power for the time being. Solution: --apply external power to prog. the FPGA --shut down and restart or restart the host i.e bus enumeration (FPGA remains configured,since we have applied external power ) --so host will detect FPGA board on PCI bus To manage the trade off b/n configuration time and bus enumeration time, there are other solutions like CvP and FPPX32 But, CvP is not supported by Gen3 X8 mode We are trying to program the FLASH using PFL.
6 PCIe Control DIP Switch SW setting: OFF OFF ON ON
7 JTAG Control DIP Switch SW setting: ON ON ON ON
8 Board setting DIP Switch SW setting: OFF ON ON OFF
9 Jungo APP results
10 Gen1 x8 Avalon ST reference design1: Results
11 Memory Read/Write
12 Interrupt
13 Data Passed the protocol layer
14 Gen2 x8 Avalon ST reference design1:results
15 Configuration space header(registers)
16 Configuration space header(registers)
17 Configuration space header(registers)
18 Memory Read/Write(error)
19 Memory Read/Write
20 Interrupt
21 Gen3 x4 Avalon ST reference design1:results
22 Memory Read/Write
23 Interrupt
24 Configuration space header(registers)
25 Configuration space header(registers)
26 Results Result of reference design1 using Jungo app(see jungo_app_results section) Memory RD/WR(32/64 bit) Interrupt Configuration Header Gen1 X8 Yes, both 32 and 64 bit RD &WR successful Listen to Interrupt failed Shows the header Gen2 X8 Yes, both 32 and 64 bit RD &WR successful Listen to Interrupt failed Shows the header Gen3 X4 Yes, both 32 and 64 bit RD &WR successful Listen to Interrupt failed Shows the header 1. We have tested the memory read and write functionality(32 bit and 64 bit) for each variation.memory read and write is successful except in case of Gen2 X8,where initially there are wrong memory read and write. The problem resolved when we have re-tested (done everything from step1) it later. 2. Listen to interrupt failed for each variation. Evaluating interrupt. --Implement MSI-X option is off in Capabilities register > MSI-X Capabilities 3. Show the Configuration space register (header) for each variation.
27 PCIE DMA APPLICATION
28 Design summary and Link training status For Gen2 X8-5Gbps
29 Write only/7 iterations/transfer length= bytes look the performance
30 Write only/2 iterations/transfer length=100 bytes look the performance**
31 Read only/5 iterations/transfer length= bytes look the performance
32 Read then write/5 iterations/transfer length= bytes look the performance
33 Write then Read/5 iterations/transfer length= bytes look the performance
34 Read and write /5 iterations/transfer length= bytes look the performance
35 EP configuration space registers
36 Scan the Motherboard PCI BUS Altera board
37 EP memory write
38 EP memory write
39 Results Result of reference design1 (gen2 X8) using DMA app 1. Performance is same for write only, read only, write then read, read then write,write and read 2. Performance degraded when the transfer length reduces from byte to 100 bytes --- due to the increasing ratio of header versus payload data and partly filled PCIe packets 3. App fetches board settings, PCI bus of motherboard,ep configuration space register information 4. App reads and writes to the target memory. 5. Link training status gives some other indication. The theoretical maximum throughput is calculated using the following formula: Throughput % = payload size / (payload size + overhead) For a 256-byte maximum payload size and a three dword TLP header (or five dword overhead), the maximum possible throughput is (256/(256+20)), or 92%.
40 Benchmark results 1 The following tables list the performance of x1, x4, and x8 operations with the Stratix V GX FPGA development board for the Intel i7-3930k 3.8 GHz Sandy Bridge-E processor using reference design1. The table shows the average throughput with the following parameters: 100 KByte transfer 20 iterations A 256-byte payload Maximum 512-byte read request 256-byte read completion In CRU,input data stream for single DMA ch is 3200 MB/s
41 DMA results of RUN2 (Thanks to Budapest Team) --SandyBridge architecture having the PCIe endpoint implemented directly in the CPU against a Ne-halem architecture where PCIe is connected using an IO-Hub. --Both architectures show decreased transfer rates for small event sizes due to the increased overhead into the ReportBuffer, the increas-ing ratio of header versus payload data and only partly filled PCIe packets. --is sum equal to 12*DMA transfer rate of one ch? --independent chs??
42 PCIE & CRU Gathered basic idea of PCIe w.r.t. our requirement based on Erno s view 1. PCIe is a BUS protocol, so multiple components can share it --multiple GBT links can share the PCIe BUS 2. Two types of BUS protocol-ep and RP --CRU will use EP BUS and O2 will use RP BUS protocol 3. O2 will see CRU (PCI40)as a piece of HW on PCI BUS --multiple FW blocks of CRU will be accessed via BAR registers --CSRs(contains BARS) will be mapped to system memory --Thus, we can access the FW blocks (registers) of CRU via application program (running on computers) by simple system memory RD and WR 4. To speed up data transfer, we need DMA(minimum processor intervention) --processor handover the memory transfer request to DMA and after successful transfer, DMA sends an ack. to processor --multiple GBT links send the data to DMA controllers --DMA controllers manage the data transfer b/n CRU and system memory through PCI BUS --DMA controller is master on that PCI BUS, so, multichannel bus master DMA term is used (from CRU development status slide,18 th feb,2015) 5. PCIE configuration space is 256 byte space
43 Future plans More precise requirement analysis of MC BM DMA ---data flow,interfaces,architecture Comparison table module required and modules available with Altera More DMA performance test with available reference design Study the DMA controller
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