Read-out of High Speed S-LINK Data Via a Buffered PCI Card

Transcription

1 Read-out of High Speed S-LINK Data Via a Buffered PCI Card A. Guirao Talk for the 4 th PCaPAC International Workshop - This is the paper copy version of the presentation- Slide 9th is repeated due to an animation CERN- EP division, ED Electronics group A.Guirao, F. Bal, M.E. Castro, H.Müller, K. Wyllie, CERN S.Jolly, Imperial College London F.Ballester, UPV 1

2 Contents Introduction to project requirements Minimizing a previous test system What the PC architecture and PCI offer The concept of the new solution Building the real system S-LINK Front-end electronics PCI hardware readout controller Software control interface Performance Conclusions and outlook 2

3 Project Requirements Laboratory test system for LHCb RICH Pixel Chips Test system on-line within 3 months 40MHz clock rate 1MHz event-rate, 32 DWORDs burst per event Inexpensive Flexible functionality Portable and handy different applications Chip characterisation Wafer testing Module (Photodetector) testing Testbeams 3

4 Minimizing a PIXEL chip test system CRATE READOUT READOUT CARD CARD I/O I/O BACKPLANE BUS READOUT CTRLER (CPU) DAQ computer DETECTOR DETECTOR (PIXEL CHIP) Solution for the previous version of the pixel chip (10MHz test system) New solution PCI BUS CTLER I/O CTLER I/O DAQ computer 4

5 The PC architecture and PCI Advantages: CPUs and many hardware resources available Most common and familiar bus architecture FPGA support Any conventional OS works with the PCI Low cost Partitionable (several controllers per bus) PCI cpci available Drawbacks: Limited space for electronics Limited power 5

6 Concept of the new solution HARDWARE SOFTWARE READOUT CONTROLLER PCI APPLICATION LAYER I/Os FPGA HAL DLL/module Custom protocol ON-BOARD MEMORY SYSTEM HARDWARE SYSTEM MEMORY HOST BRIDGE CPU 6

7 Building a real system 1 2 7

8 S-LINK Front-End electronics Single mode (32 dwords for LHCb) or multievent readout mode (up to 16 events per trigger) Adaptation of S-LINK bus width for LVDS serializers 8

9 PCI Readout Controller The FLIC card Standard PCI card small, familiar Easy to use (Plug&Play) General Purpose solution Mezzanine cards interchangeable Custom HW interface (FPGA, HDL) Low cost Large data buffer local memory becomes system memory 9

10 PCI Readout Controller The FLIC card Standard PCI card small, familiar Easy to use (Plug&Play) General Purpose solution Mezzanine cards FPGA interchangeable LOGIC Custom HW interface (FPGA, HDL) Low cost Large data buffer local memory becomes system memory 10

11 LabView Analysis and Interface Existing analysis software for the chip Interface with commercial cards (JTAG controller) Need of developing a Windows TM driver for the FLIC Existing support for Linux Readout Software 11

12 Performance LHCb pixel mode 40MHz clock 32 dwords burst DATA SOURCE SLINK REAL-TIME SLINK HARDWARE SOFTWARE 132MB/s payload FLIC input SLINK FLIC PCI Jungo driver OFFLINE 132MB/s SDRAM 64MB MEMORY BANKS FLIC specific DLL LabView interface 3MB/s 12

13 Conclusions and Future Conclusions A test system has been built based on PCI controller 40MHz performance reached More systems have been reproduced in short time Low cost per system Works under LabView Logically compatible with the previous test system Easy maintenance and upgrading Future possibilities Scalability: several readout controllers per PC Higher speed in the software domain (DMA engines) More complex controllers may fit in larger FPGAs 13

14 Thanks! 14