System Buses Ch 3. Computer Function Interconnection Structures Bus Interconnection PCI Bus. 9/4/2002 Copyright Teemu Kerola 2002

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1 System Buses Ch 3 Computer Function Interconnection Structures Bus Interconnection PCI Bus 1

2 Computer Function von Neumann architecture memory contains both instruction and data Fetch-Execute Cycle CPU System bus Memory (käskyn nouto ja suoritus sykli) Figs 3.3, 3.9 2

3 I/O control CPU executes instructions and with those instructions guides I/O modules control and data registers in I/O modules I/O modules give feedback to CPU with control and data registers, but only when CPU is reading them! Memory CPU Device driver Device Bus I/O Module process Device 3

4 I/O Control Interrrupts allow I/O modules to give feedback to CPU even when CPU is doing something else Memory CPU Device Bus I/O Module interrupt signal wakeup, I have great news! DMA allows I/O modules to access memory without CPU s help 4

5 CPU von Neumann Bottleneck System bus Memory I/O All components communicate via system bus Each component has its own inputs/outputs System bus must support them all (von Neumann pullonkaula) Fig Fig

50-100 lines (wires) System Bus address data control other: power, ground, clock Performance

6 lines (wires) System Bus address data control other: power, ground, clock Performance bandwidth, (väyläkapasiteetti) how many bits per sec? propagation delay? (päästä päähän viive) 6

7 Bus Configurations One bus alone might be very long large end-to-end signal time serious von Neumann bottleneck all devices use similar speeds slowest device determines speed used Hierarchy of buses can maximize speed for limited access closer to CPU lower speed general access I/O further away from CPU 7

8 Hierarchy of Buses Typical Pentium II system PCI to SCSI bridge (Tanenbaum, Structured Computer Organization, 4th Ed.) 8

9 [ LX6 ] - Pentium II Processor Based Motherboard CPU AGP IDE PCI ISA USB keyboard/mouse parallel serial 9

10 Bus type Bus Design Features (3) dedicated, multiplexed (aikavuorottelu) Arbitration method centralised, distributed bus controller, arbiter Timing synchronous asynchronous (vuoronvalinta) (keskitetty, hajautettu) (vuoronantaja) (asynkrooninen, epäsynkrooninen) 10

11 Synchronous timing All same speed devices All synchronized with a clock signal Slowest device determines speed Can make assumptions on when some other device will do something, or how fast it will do it 1 or 2 clock cycles to do it? Fig (Fig (a) [Stal99]) 11

12 Asynchronous timing No need to have same speed devices No synchronizing clock signal Timing determined only with change of signal levels Synchronize with signals (wires) read, write, ack, Speed determined by devices in action Can not make assumptions on when some other device will do something, or how fast it will do it Fig (Fig (b) [Stal99]) 12

13 Bus Design Features (cont) Bus width address, data Data transfer types read, write multiplexed & non-multiplexed operations read-modify-write E.g., for indivisible increments (multiproc. env.) read-after-write E.g., for check that write succeeds (multiproc. env.) block Fig long delay for interrupt handling? (Fig [Stal99]) 13

14 Example Bus: Industry Standard Architecture (ISA, or PC-AT) Bus type: dedicated Arbitration method: single bus master Timing: asynchronous own 8.33 MHz clock, 15.9 MBps max data rate, 5.3 MBps in practice Bus width: address 32, data 16 Data transfer type read, write, read block, write block 14

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16 Example: Peripheral Component Interconnect (PCI) Bus Bus type: multiplexed Arbitration method: centralised arbiter Timing: synchronous, own 33 MHz clock Gbps (265 MBps) max data rate Bus width: address/data 32 (64), signal 17 Data transfer type read, write, read block, write block max 16 slots (devices) 16

17 PCI Configurations Hierarchy Fig (Fig [Stal99]) Bridge to internal/system bus allows them to be faster (with different bus protocol) Bridge to expansion buses allows them to slower (with different bus protocol) 17

18 PCI card: 49 Mandatory Signals (6) 32 pins for address/data, time multiplexed 1 parity pin 4 pins for command type/byte enable E.g., 0110/1111 = memory read/all 4 bytes System pins (2): clock, reset Transaction timing & coordination pins (6) Arbitration pins (2 for each device) to PCI bus arbiter: REQ, GNT Error pins (2): parity, system 18

19 PCI Bus 41 Optional Signals (4) Request interrupt pins (4 pins for each dev) Cache support pins (2) for snoopy cache protocols CPU CPU bridge cache RAM bridge PCI bus 32 pins for additional multiplexed address/data plus 7 control/parity pins 5 test pins cache RAM 19

20 PCI Bus Transaction (4) Bus activity is in separate transactions Each transaction preceded by arbitration Fig (Fig [Stal99]) central arbiter (e.g., First-In-First-Out) determines initiator/master for transaction Transaction is executed Bus is marked ready for next transaction 20

21 PCI Transaction Types (5) Interrupt Acknowledge READ interrupt parameter (e.g., subtype) for interrupt handler Special Cycle broadcast message to many targets Configuration Read/Write Read/Update (Write) device configuration data Dual Address Cycle use 64 bit addresses in this transaction I/O or memory read/write (line, multiple) 21

22 PCI Read Transaction (no anim) Fig (Fig [Stal99]) 22

23 a) start trans frame, d) ack address, set data, set & indicate data set addr, set trans. CPU type indicate Reads valid from data Memory data ready, read (14) b) recognise address, find data data ready, read e) sel next bytes set & indicate data g) not ready: hold c) select bytes, f) need more time, h) ready for last block: indicate ready to receiveindicate not valid data end frame and stop hold Initiator CPU action Target memory action data ready, read get ready for next All ready for new transaction get ready for next (Fig [Stal99]) All Fig. ready 3.23 for new transaction 23

24 Arbitration: A and B want bus Fig Mostly just arbitration signals shown here (Fig [Stal99]) 24

25 a) A wants bus b) B wants bus c) A granted bus knows that it has bus and bus is available A action B action Arbitrator action d) starts frame, Arbitration: requests for next A for and next trans. B want no more bus req. (10) transaction Sees that both still want it e) Grants bus to B A s target reads data g) starts frame f) marks last frame transfer, marks data ready Sees that only A wants it All ready for new trans All ready Fig for new trans, (Fig. granted 3.24 [Stal99]) for B, B knows that it has bus 25

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27 PCI Express: New Bus to Replace PCI Code name Arapahoe or 3GIO Prevent bus bottleneck between fast CPU and memory of the future Arapahoe Work Group Compaq, Dell, IBM, Intel and Microsoft Will replace PCI as industry standard late 2003? low-end 2004? high-end 2005? PCI devices will work with PCI Express Speedup 30x as compared to std PCI at least 8 GB/s vs. 264 MB/s Scalable capacity per device (pin count, speed) 27

28 -- End of Chapter 3: System Buses -- (PCI card - connectors also on other side, some pins not used by this card) 28

Bus (Väylä) Stallings: Ch 3 What moves on Bus? Bus characteristics PCI-bus PCI Express

Lecture 2 Bus (Väylä) Stallings: Ch 3 What moves on Bus? Bus characteristics PCI-bus PCI Express Bus (Sta06 Fig 3.16) For communication with and between devices Broadcast (yleislähetys): most common Everybody