ECE 485/585 Microprocessor System Design

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1 Microprocessor System Design Lecture 15: Bus Fundamentals Zeshan Chishti Electrical and Computer Engineering Dept. Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F.

2 Buses Part 1

3 Topics: Introduction Why study buses? What are buses? Overview and definitions Buses Bandwidth Arbitration Enumeration and Configuration Compatibility (Backward and Forward) Parallel Buses PC Bus Evolution PCI Bus Serial Buses Characteristics and tradeoffs USB

4 Why Study Buses? Bus design plays a huge role in computer architecture Performance, Cost Flexibility, Reliability Quality of Service Source: Block diagram of IBM PC Motherboard (IBM Corp)

5 Why Study Buses (cont d) Throughput of microprocessor-based systems On-chip buses (e.g. processor/cache, intra-cpu, multi-core) Chip-to-Chip Memory bus (connecting one or more processors to memory subsystem Inter-processor communication Board-to-Board Chassis-to-Chassis I/O buses to connect peripherals (I/O or peripheral buses) System-to-System communication (networking) Network-to-Network (Internetworking) Our Objectives: Learn basic terminology related to buses Examine evolution of buses in microprocessor-based systems Study state-of-the-art PC buses Focus on common issues (e.g. arbitration, error handling, enumeration)

among agents Rules for how different agents can connect to the bus Rules for communicating across the bus (protocol) Bus

6 Bus Basics CPU initiates all transactions (bus master). Control and addresses from CPU, Data is bi-directional The bus provides: Physical interconnection structure that s shared among agents Rules for how different agents can connect to the bus Rules for communicating across the bus (protocol) Bus arbitration Determines which of two or more agents becomes the bus master I/O device may initiate transaction. Competition for bandwidth, initiation, Process to discover all devices on the bus

7 Bus Definition Includes Mechanical specification Connectors, plugs, receptacles Cable length Electrical specification Voltage, termination Timing and signaling specification Clocking, timing Handshaking Protocol Packet numbering/sequencing Arbitration Error handling Addressing Initialization/Configuration

8 Bus Design Tradeoffs Topology Multi-drop vs. Point-to-Point Data Width Serial vs. Parallel (number of bits) Speed Multiplexing Will signals have more than one use (e.g. address/data lines) Clocking Asynchronous vs. Synchronous Arbitration How does a device (agent) become the bus master?

9 Bus Design Tradeoffs (cont d) Addressing How are agents uniquely identified? How many agents/endpoints can be defined? Error Detection and Error Handling Identification (Enumeration)/Configuration Static (ex: one CPU <-> one memory) Dynamic At initialization (ex: PCI) Hot pluggable, plug-and-play (ex: USB)

10 Bus Concepts and Terms Bus-cycle time Number of transfers/second Bandwidth Amount of data/transfer Total Bus Bandwidth Maximum number of bytes/second Theoretical Bandwidth Achievable w/o considering bus conflict, errors, protocol overhead Actual Bandwidth Realizable bandwidth when these factors considered Latency Delay from initiation to start of response Concurrency Ability to do more than one thing at a time (like in a CPU) Achieved via replication or pipelining Replication (e.g. wider bus -> more bytes transferred at a time Pipelining (e.g. multiple simultaneous transactions

11 Units Revisited Bits vs. Bytes B (upper case) is used for bytes (ex: 60 MB/sec) b (lower case) is used for bits (ex: 480Mbps) What is 1K? Communication/data transfer (decimal) 1K = M = MB/sec = 10 6 bytes/second Memory (binary) 1K = 2 10 = M=2 20 = 1,048,576 Disk (depends) If you re an engineer binary If you re in marketing/sales decimal 128 GB drive (137 x 10 9 bytes) (2 28 sectors x 512 bytes/sector)

12 Calculating Bandwidth Theoretical Bandwidth Data Width x Speed 32 bits x 66 MHz = 4 bytes x 66 MB/sec = 264 MB/sec Actual Bandwidth is less because you have to factor in: Protocol how many cycles for a transfer? Cycle(s) to send address Cycle(s) to fetch data (device latency) Cycle(s) to transmit data Arbitration and Error phases? Delayed Response and Retries Payload efficiency

13 BOTEC * Bus Bandwidth Calculations ISA Bus 8 MHz, 16-bits (2 bytes) wide, 4 cycles/transfer Assuming no wait states (8Mcycles/sec x 2 bytes/transfer) / 4 cycles/transfer = 4MB/sec 100 BaseT Ethernet 100Mb/sec 100Mb/sec / 8 bits/byte = 12.5MB/sec Video Card 800 x 600 pixels, R/G/B = 8 bits, 30 frames/sec (800 x 600 x 3 bytes/frame) x 30 frames/sec = 43.2MB/sec * Back-of-the-envelope calculation

14 Bus Arbitration What happens when more than one agent wants control of the bus (e.g. to become the bus master)? Bus arbitration decides which agent gets to control the bus next Arbitration can be: Centralized Daisy chained (VME) Dedicated lines (PCI) Decentralized Self-selection (Apple Mac NuBus, FSB, SCSI) Collision detection (Ethernet)

15 Centralized Daisy Chain Arbitration Advantage: Simplicity Disadvantages Low priority devices can be locked out indefinitely (starved) Latency daisy chain GRANT signal limits bus speed

16 Centralized Parallel Bus Arbitration

17 Arbitration Policy Goals Priority Highest priority agent should be serviced first Fairness Even lowest priority agent should not be locked out Guaranteed worst case latency Priority can be static or dynamic

18 Ex: An Unbiased Arbiter Consider three bus agents (A, B, C) Assign an initial priority (e.g. A, B, C) After a request is granted that agent s priority is set to the lowest priority If a single request is received it is granted If two or more requests are received the agent with the highest priority is granted the bus

19 Ex: Unbiased Arbiter Implementation (cont d)

20 Ex: Unbiased Arbiter Rotating Priority Problem: Number of states grows at n! where n is the number of agents Ex: 8 agents = 8! = 40,320 states. There must be a simpler way!! Eliminate history but greatly reduces # states (to 3) Priority follows same algorithm Transition to state w/ winning agent at lowest priority

21 Ex: Unbiased Arbiter Rotating Priority (cont d) No request can be outstanding for more than n cycles where n is the number of agents (states). Worst case latency is no worse than the previous scheme

22 Ex: Unbiased Arbiter Round Robin Observe the logic in computing the next state it s just a counter or circular shift register

23 Device Connection Task: Determine what devices are present Identify requirements and capabilities Latency, bandwidth needs, address space Determine or assign (base) address Allocate resources (e.g. buffers) Approaches: Completely static (ex: think back to week 1): One processor/one memory Processor and fixed address I/O device (hardwired decoding) Fixed at boot time (ex: PCI) Device discovery BIOS enumeration Alternative (initial) means of addressing devices Plug and Play (ex: USB) Dynamic discovery

24 Compatibility High (huge!!!) cost of change Large installed base/investment Hardware, software, expertise Backward compatibility New system/device will operate in context of old environment Ex: High speed USB 2.0 device must operate on USB 1.0 connectors, hubs Forward compatibility New system designed so that old devices/systems will operate in new environment Ex: PCI-X bus allows PCI devices to connect

25 Common PC Buses Legacy Local/System Buses I/O Buses and Others PC Bus (ISA 8-bit) USB 2.0, 3.0 IBM MCA (microchannel) IDE, EIDE, SATA ISA (PC/AT) SCSI EISA (Extended ISA) Firewire VESA Local Bus (VLB) PCMCIA, CardBus Contemporary Local/System Buses Infiniband HyperChannel PCI PCI Express PCI-X Quickpath AGP (no new designs) Front Side Bus (Intel)

Buses. Disks PCI RDRAM RDRAM LAN. Some slides adapted from lecture by David Culler. Pentium 4 Processor. Memory Controller Hub.

Buses. Disks PCI RDRAM RDRAM LAN. Some slides adapted from lecture by David Culler. Pentium 4 Processor. Memory Controller Hub. es > 100 MB/sec Pentium 4 Processor L1 and L2 caches Some slides adapted from lecture by David Culler 3.2 GB/sec Display Memory Controller Hub RDRAM RDRAM Dual Ultra ATA/100 24 Mbit/sec Disks LAN I/O Controller