Overview of Intel 80x86 µp

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1 CE444 ١ ٢ 8088/808 µp and Supporting Chips Overview of Intel 80x8 µp ٢ ١

2 8088/808 µp ٣ Both are mostly the same with small differences. Both are of bit internal Data bus Both have 0 bit address bus Capable of addressing M of memory 0 = 048 Made of 9000 NMOS trans. In 40 pins packages ٣ 8088 Differences ٤ 8088 has bit internal Data bus but it has externally 8 bit Data bus 8088 designed after 808 to be capable of using the 808 peripherals Use DIP (dual in-line) packaging technique ٤ ٢

3 808 µp ٥ NMOS trans. 4 address pins pins for Data Use LCC (Leaded Chip Carrier) technology instead of DIP Runs all instruction of the 8088/808 plus new instructions and capabilities ٥ 8038 µp ٦ 3 bit registers 3 bit address bus Can address 4 G of memory CMOS trans There are tow popular versions: 8038 DX 8038 SX ٦ ٣

4 8038 SX ٧ Internally 3 bit Externally bit data bus 4 bit address bus Compatible with 8 Capable of running 3 bit software written for the 38 ٧ 8048 µp ٨. million CMOS trans. 8 pin PGA 3 bit µp Capable of addressing 4 G Integrated the 8038 math coprocessor and 8 K bytes of cache memory into a single chip ٨ ٤

5 8048 SX ٩ Exactly like the 8048 except that it does not contain the math coprocessor Instead a math coprocessor for the 8048sx is available on a separated chip which is the 8048SX ٩ Pentium ١٠ 3 BICMOS million trans 0 and MHz speed Include separate 8 k bytes cache for data and code 3 bit register 3 bit address bus 4 bit bus 3 pin PGA package ١٠ ٥

6 ١١ ١١ ١٢ ١٢ ٦

7 ١٣ 8088/808 µp Data bus Internally both are bit bus Externally» 8088 has 8 bit bus AD0 to AD» 808 has bit bus AD0 to AD ALE: address latch enable is needed Address bus : 0 pins Needs a latch to latch the address Most widely used latch is 4LS33 ١٣ Data Bus ١٤ Data Bus of 808 Data Bus ١٤ AD4 AD3 AD AD AD0 AD9 AD8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC AD A/S3 A/S4 A8/S A9/S BHE/S MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET ٧

8 ١٥ Data Bus of 8088 Data Bus ١٥ A4 A3 A A A0 A9 A8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC A A/S3 A/S4 A8/S A9/S SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET ١٦ INTR: Interrupt Request INTR: Interrupt Request Active high level-triggered input Monitored by µp at the last clock cycle after each instruction. BHE: Bus High Enable Used with 8 to distinguish between high and low byte NMI: Nonmaskable interrupt Edge triggered input signal from low to high Input to mp. Cause µp to jump into interrupt vector after finishing current instruction Can not be masked by software ١٦ AD4 AD3 AD AD AD0 AD9 AD8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC AD A/S3 A/S4 A8/S A9/S BHE/S MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET ٨

9 ١٧ Clock Mp require a very accurate clock for synchronizing. Intel has designed 884 clock generator CLK is an input and connected to 884 clock generator Any irregularity cause the CPU to malfunction ١٧ AD4 AD3 AD AD AD0 AD9 AD8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC AD A/S3 A/S4 A8/S A9/S BHE/S MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET ١٨ Reset Terminate present activity of mp Input to mp Active high Signal comes from 884 After reset mp will contains the following Data: CPU Contents CS FFFFH DS 0000H SS 0000H ES 0000H IP 0000H FLAG CLEAR QUEUE EMPTY ١٨ AD4 AD3 AD AD AD0 AD9 AD8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC AD A/S3 A/S4 A8/S A9/S BHE/S MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET ٩

10 ١٩ READY: Input signal Used to insert a wait state for slower memories and IO. It inserts a wait state when it is low ١٩ AD4 AD3 AD AD AD0 AD9 AD8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC AD A/S3 A/S4 A8/S A9/S BHE/S MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET ٢٠ TEST Input signal FROM 808 Coprocessor ٢٠ AD4 AD3 AD AD AD0 AD9 AD8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC AD A/S3 A/S4 A8/S A9/S BHE/S MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET ١٠

11 Minimum Mode Vs. Maximum Mode ٢١ The function of pins 4 through 3 of 8088 and 808 varies depending upon whether the mp is in max or min mode AD4 AD3 AD AD AD0 AD9 AD8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC AD A/S3 A/S4 A8/S A9/S BHE/S MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET ٢١ Pin specifying the operation Mode Low Maximum Mode High Minimum Mode Minimum Mode Vs. Maximum Mode ٢٢ The function of pins 4 through 3 of 8088 and 808 varies depending upon whether the mp is in max or min mode AD4 AD3 AD AD AD0 AD9 AD8 AD AD AD AD4 AD3 AD AD AD0 NMI INTR CLK VCC AD A/S3 A/S4 A8/S A9/S BHE/S MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Min Mode Logic ٢٢ Max Mode Logic 0 RQ / GT0 RQ / GT LOCK S S S0 QS0 QS ١١

12 ٢٣ Min Vs Max Modes In Min Mode: Pins 4 3 are used as memory and I/O control signals The control signal are generated internally by 88, 8 Thus Min Mode is More cost efficient Pins 4 3 of 88,8 are functioning similarly to 8 Thus 808 peripheral can be used with this mode. ٢٣ ٢٤ Min Vs Max Modes In Min mode the pins 4 3 function as shown in the following table: Pin INTA ALE DEN DT / R MEM / IO (8) Or IO / M (88) WRITE HLDA HOLD ٢٤ Function ١٢

13 ٢٥ Pins 4 3 in Min Mode (4) INTA interrupt acknowledge Active low output signal Inform interrupt controller that an interrupt has occurred And the vector number is available on the lower 8 lines of the data bus. ٢٥ ٢٦ Pins 4 3 in Min Mode () ALE address latch enable Active high output signal Indicate that a valid address is available on the external address bus () DEN Data Enable Active low output signal Enable 4LS4, which allows isolation of the CPU from system Bus ٢٦ ١٣

14 ٢٧ Pins 4 3 in Min Mode () DT / R Data Transmit Receive Active low output signal Used to control the Data Direction of data flow through 4LS4 tranceiver ٢٧ ٢٨ Pins 4 3 in Min Mode (8) IO / M ( 88) or IO / M ( 8) Memory or Input/output Indicate whether address bus is accessing memory or input / output device See the difference between 88 and 8 ٢٨ ١٤

15 ٢٩ Pins 4 3 in Min Mode (9) WR write Active low output signal Indicating that Data on the bus is being written to memory or I/O device (30) HLDA hold acknowledge Active high o/p signal used after HOLD. Indicate that CPU allows to the DMA to Use buses. ٢٩ ٣٠ Pins 4 3 in Min Mode (3) HOLD Hold Active high input from DMA controller Indicates that device requesting to control the local buses SSO status line For 88 only, an output signal that can be used along with the IO/M and DT/R to decode the status of the current bus cycle. ٣٠ ١٥

16 ٣١ Min mode bus design for the 88/8 in min mode some control signal must be generated using logic gate. In max mode these signal are provided by the /8 in min mode provides 3 signals RD, WR, AND IO / M (Or M / IO ) Using these 3 signal 4 important signal must be generated. ٣١ Min mode bus design ٣٢ These signals are shown in the following table: RD WR IO / M 0 0 X ٣٢ MEMR MEMW IOR IOW Signal Never Happened ١٦

17 Min mode bus design ٣٣ WR IO / M RD ٣٣ IOW MEMW MEMR IOR ٣٤ Min mode bus design ٣٤ ١٧

18 Min mode bus design ٣٥ ٣٥ Basic Buses of 8088 Min mode ٣٦ ٣٦ ١٨

19 ٣٧ 8088, 808 in Max Mode In Max Mode Some control signal are generated externally by the 888 bus controller Some pins are used for new features available only for Max Mode Mostly used when CPU is used with Math Coprocessor IBM PC/XT and compatible use 88, 8 with 808 coprocessor ٣٧ 8088, 808 in Max Mode ٣٨ (4 and ) QS0 and QS queue Status Give information to the system about the Queue inside mp at any given time In IBM PC these pins are connected to 808 to synchronize it with 8088 The following table describe their function ٣٨ ١٩

8088, 808 in Max Mode ٣٩ (, and 8) So, S And S Status signal Connected to 888 which will use them to produce all control signal such as those shown in table ٣٩ 8088, 808 in Max Mode ٤٠ (9 ) LOCK Pin

20 8088, 808 in Max Mode ٣٩ (, and 8) So, S And S Status signal Connected to 888 which will use them to produce all control signal such as those shown in table ٣٩ 8088, 808 in Max Mode ٤٠ (9 ) LOCK Pin Active low o/p signal Used to prevent other processor or devices from gaining control on the buses Activated by LOCK prefix in the instruction of the assembly program (30, 3 ) RQ / GT0 and RQ / GT request Grant Bidirectional Lines Allow other processors to gain control on the bus In IBM PC, RQ / GT0 is connected to high making it disabled and RQ / GT Is connected to 808 ٤٠ ٢٠

21 Pipelining ٤١ ٤١ Pipelining ٤٢ Fetch Fetch Decode Fetch 3 Decode Exec. Fetch 4 Store Decode Decode 3 4 Exec. Memory request Exec. 3 Fetch Idle Exec. 4 ٤٢ Fetch Decode Idle Load Decode Exec. Memory request Fetch Idle Exec.... Decode Idle... Exec. Bus Instruction Unit ٢١

22 ٤٣ Fetch Execute Fetch Execute ٤٣ Fetch Execute Fetch Execute ٢٢

Chapter NINE 8088,80286 MICROPROCESSORS AND ISA BUS

Chapter NINE 8088,80286 MICROPROCESSORS AND ISA BUS OBJECTIVES this chapter enables the student to: State the function of the pins of the 8088. List the functions of the 8088 data, address, and control