Proposal for Digitizer-to-SLINK Interface Card

Transcription

1 Proposal for Digitizer-to-SLINK Interface Card J. Pilcher (for Haifeng Wu) 10-Sept-1999

2 Overview Located in drawers (1 interface board/drawer) Input from 8 digitizer boards (16 DMU chips) Output to ROD modules via SLINK UP to Higher Level ROD Slink/ G-link Digitizer Digitizer Digitizer Digitizer Interface Board Digitizer Digitizer Digitizer Digitizer

3 Goals for new design No timing adjustments needed from digitizer boards Easy setup and reliable long-term operation Complete 2-fold redundancy to RODs Reviewers questioned single point of failure in drawer interface Data formatted in 32-bit words from one DMU at a time ( natural format ) Transparent format for easier debugging & easier spotting of failures

4 Goals for new design (cont.) Can order sequence of output channels according to drawer geometry, or tower geometry Simplifies interface with ROD SLINK/GLINK interface built into board No mezzanine card Much more compact 640 Mb/s capability (standard) 346 Mb/s required for TileCal MHz LVL1A rate) Derandomizing buffers on digitizer boards

5 Goals for new design (cont.) Use no custom chips Avoid high development costs and long delays Programmable commercial devices EPLD or FPGA like Altera, Xilinx, Actel Studies so far with Altera 20K100 (100K gates, 3ns gate delay)

6 Organization Dual structure of interface card for redundancy All complexity in Interface Logic chips LVDS Driver 8 TTC signals PECL convert Optical receiver From TTC flow control LV DS O R Interface Logic SLINK logic G-link Tx S C To ROD All si g nal s From 8 digitizer LV DS Interface Logic SLINK logic G-link Tx S C To ROD LVDS Receiver Figure 2: Block diagram of interface board.

7 Organization Serial-to-parallel (SP) input stage for each DMU Individual data clocks from each digitizer board Data time-aligned by Pipe Data accumulated in Input Buffer (2 page buffer) Data delivered to Output FIFO in desired order 3 (clock, ctrl_in, wen_in) 3 clocks flow_ctrl 5(reset_in, test_in) + power_on Data clock ctrl_in wen_in Clock Master Reset Flow Controller SP Converter Pipe 20MHz Address Machine Data Constructor Input Buffer Address Machine Output FIFO Output Controller M U X 40MHz UWEN UCLK UCTRL LFF LDOWN UDATA To Slink SP Converter Pipe Input Buffer Output FIFO Figure 3: Block diagram of the interface logic chip

8 Serial-to-Parallel Converter Pair of bits from serial inputs every 25 ns 32-bit output every 400 ns SP converters asynchronous in pairs (8 input clocks) SP Convertor Reset from Flow controler wen_in Preset ctrl_in clock_in Logic controller output_enable data2 Data_ready shift_en counter_en clear 4 bit Counter data1 Comparator data_n 16 bit shift register 16 bit word Format 32 bit words 32 bit word data_n+1 16 bit shift register 16 bit word (according to protocol) Note: every two SP convertor share one group (wen_in, ctrl_in, clock_in) signals from one digitizer board, mean while each of them own two data input s from different DMU of the digitizer board.

9 Pipe Section 32-bit input registers loaded asynchronously Unloaded one register every 50 ns (8 in 400 ns) Input registers free after 200 ns (4 double-buffers) Pipe Reset 20MHz clock write_en data1 data_ready1 Logic controller clear count_pulse 3 bit counter write_clk 2nd_reg_en 32 bit word to the input buffer MUX data8 data_ready8

10 Master Clock Section Choose one out of 3 possible clocks at reset time Each interface logic chip has one of these (redundant) Clock Master clock1 clock2 clock3 counter counter counter count_en Logic controller MUX Reset During reset circle the logic controler enables 3 counters, and compare the counts, it picks the clock that equals or only has1 count differentto one of other two. The default clock is clock1. 1/2 clock20 clock40

11 Status Most VHDL code written and tested Must fully simulate timing margins

12 Planning Requesting concept approval by TileCal Submit proposal for funding to US ATLAS Additional source of funding for readout Action in 6 months? Continue design and prototyping Details to be agreed to with Stockholm Clearly written interface specifications needed System demonstration test with prototype within 1 year Production would follow