The MROD. The MDT Precision Chambers ROD. Adriaan König University of Nijmegen. 5 October nd ATLAS ROD Workshop 1

Transcription

1 The MROD The MDT Precision Chambers ROD Adriaan König University of Nijmegen 5 October nd ATLAS ROD Workshop 1

2 Contents System Overview MROD-0 Prototype MROD-1 Prototype Performance Study FE Parameter Loading & Initialization Names 5 October nd ATLAS ROD Workshop 2

3 System Overview TDC 1 18 x TDC 18 Chamber CSM Tower TDC 1 6 x MROD 1.28 Gbit/s S-Link to ROB 18 x CSM TDC 18 5 October nd ATLAS ROD Workshop 3

4 TDC Functionality 24 channels, 0.78 ns bin size entirely data driven: records time stamp for each hit (leading and/or trailing edges) stores hits in internal derandomizing buffer upon receipt of a L1A, it ouputs the relevant hit data words on a serial output link (40 Mbit/s) with header and trailer words 5 October nd ATLAS ROD Workshop 4

5 CSM Functionality 40 Mbit/s Data/Strobe from TDC 40 Mbit/s Data/Strobe from TDC 1 Start bit 32 Data bits 1 Parity bit 1 Stop bit ns = 875 ns Serial to Parallel & Clock Domain Separator 18 x Separator Serial to Parallel & Clock Domain Separator 1 S 18 CSM 1 Gbit/s (S-Link) 1 Separator word (S) 18 TDC data words 19 words in 875 ns 87 MB/s 5 October nd ATLAS ROD Workshop 5

6 Separator word TDC0, word 1 (tdc 1) Check (do not store) Skip (do not store) MROD Function Build events in a partitioned memory from TDC data fragments time TDC2, word 4 TDC3, word 2 Separator word TDC0, word 1 TDC1, word 3 TDC2, word 5 TDC3, word 3 TDC2, word 3 Separator word TDC1, word 2 TDC2, word 2 (tdc 0) TDC1, word 1 TDC2, word 1 TDC3, word 1 TDC0, word 0 TDC1, word 0 TDC2, word 0 TDC3, word 0 5 October nd ATLAS ROD Workshop 6

7 MROD Throughput MROD S-Link MROD input S-Link MROD input S-Link S-Link S-Link S-Link MROD input MROD input MROD input MROD input MROD output S-Link 1.28 Gbit/s ( 128 MB/s) Average 5 hits per TDC + header + trailer = 7 words/event Per tower of 6 chambers max. 88 TDCs * words/event (= 2.4 kb/event) Worst case 100 khz L1A rate 240 MB/s per MROD Calculation based on actual tower layout (J.Chapman): max. rate < 60 MB/s per MROD 5 October nd ATLAS ROD Workshop 7

8 MROD Form Factor 9 U VME board (single slot), 6 inputs, 1 output Optionally 2 extra inputs with extension board to accommodate special towers (> 6 chambers) S-link interfaces on main board SHARC II (ADSP21160), 2.5 x faster than MROD Crate contains: 12 MRODs (12 η Segments) Max. 4 MROD Extension Boards 1 Standard (?) Crate Master with Ethernet Interface (DetDAQ) 1 TTC-Rx Interface Module 1 Busy Module?? 1 DCS Interface 192 towers: 192/12 = 16 MROD Crates (1 per ϕ Sector) 5 October nd ATLAS ROD Workshop 8

9 MROD-0 Prototype MRODIN MCRUSH sorted TDC-data over SHARC Link MRODOUT SHASLINK PCISHARC 5 October nd ATLAS ROD Workshop 9

10 MROD-0 Input Channel MCRUSH FIFO Input Tetris Register FPGA FIFO Output Control Data FIFO Length FIFO Control/Status Error signaling 1 MB ZBT Memory SHARC 6 Sharc 40 MB/s each 5 October nd ATLAS ROD Workshop 10

11 MROD-0 Output Channel SHaSLINK PCI bus PCI 9054 SHARC 6 SHARC 40 MB/s each Altera 10K10A 160 MB/s 5 October nd ATLAS ROD Workshop 11

12 (SHARC) 5 October nd ATLAS ROD Workshop 12

13 FPGA Memory SHARC VME64x MROD-1 Prototype FPGA Memory 3x (in total) Sharc Links SHARC (2x) FPGA FPGA Memory SHARC Memory TTC Interface 5 October nd ATLAS ROD Workshop 13

14 SHARC-II 5 October nd ATLAS ROD Workshop 14

15 The ADSP and the ADSP SHARCs 40 MHz / MHz CPU (SIMD mode) 512 KB / 512 KB internal memory 6 x 40 / MB/s links. Throughput of all links simultaneously is 160 / (?) MB/s, without disturbing the CPU. No handshaking on links, but hardware XON-XOFF protocol, 10 / 14 DMA channels Support for bus arbitration: at max. 6 SHARCs can be connected to a common bus without glue logic. Each SHARC can access the internal memories of each other SHARC. The SHARCs also provide support for a so-called host interface, which can act as an additional master on the common bus. Fast interrupt servicing due to the presence of shadow registers Two 40 Mbit/s / Mbit/s (at max.) synchronous serial ports Can be booted via link 4 5 October nd ATLAS ROD Workshop 15

16 MROD-1 Form Factor 9 U VME board, 6 inputs, 1 output S-link interfaces on daughter boards Input S-link daughter boards SHARC II (ADSP21160), 2 x faster than (3 for input, 2 for output processing) Altera APEX FPGAs, 200k gates TTC interface (over back plane) VME64x interface Input Input Output Motherboard 5 October nd ATLAS ROD Workshop 16

17 MROD-1 Status & Planning VHDL design of FPGAs almost finished. Modules available by 1 st April Extensive tests and performance measurements at NIKHEF. System integration tests with CSM. System integration tests with ROB and DAQ test set-up (possibly in test-beam). Read out of BOL test stand at NIKHEF. 5 October nd ATLAS ROD Workshop 17

18 MROD Performance Study MROD CSM MRODIN CSM MRODIN CSM MRODIN MRODOUT ROB CSM MRODIN CSM MRODIN CSM MRODIN 5 October nd ATLAS ROD Workshop 18

19 MROD Emulation Hardware SHASLINK CSMSIM 0 TDCdata fragment lengths MROD-0 0 MCRUSH MRODIN (3x) 4 2 sorted TDCdata sorted 3 TDCdata sorted + merged TDC-data Region-of-Interest Requests, Decision Records, etc., everything needed to run a ROBIN simulation RoIRR 2 2 SHASLINK CRUSH SHASLINK 0 RoID/ T2OD 0 4 RoIR/ T2DR 4 MRODOUT ROBIN ROBSIM 4 PCISHARC xxxxx Module type event fragment lengths via SHARC-link simulates future MROD-1 functionality optionally double/triple MRODIN output thus simulating 2 or 3 MRODINs S-Link SHARC-link (PCI-)interface to host PC 5 October nd ATLAS ROD Workshop 19

20 MROD CSMSIM MRODIN MRODOUT ROBIN ROBSIM CSM-simulator performance Event rate [khz] Words/TDC 5 October nd ATLAS ROD Workshop 20

21 MROD Performance Study Results CSMSIM MROD MRODIN MRODOUT ROBIN ROBSIM MRODIN (1x) + MRODOUT + ROBIN, 18 TDCs 180,0 160,0 140,0 120,0 Event rate [khz] 100,0 80,0 60,0 40,0 20,0 0, Words/TDC MRODIN MRODIN+MRODOUT MRODIN+MRODOUT+ROBIN 5 October nd ATLAS ROD Workshop 21

22 MROD Performance Study Results CSMSIM MROD MRODIN MRODOUT ROBIN ROBSIM MRODIN (1x) + MRODOUT + ROBIN, 6 TDCs Event rate [khz] Words/TDC MRODIN MRODIN+MRODOUT MRODIN+MRODOUT+ROBIN 5 October nd ATLAS ROD Workshop 22

23 MROD Performance Study Results CSMSIM MROD MRODIN MRODOUT ROBIN ROBSIM MRODIN (2x) + MRODOUT + ROBIN, 18 TDCs Event rate [khz] Words/TDC MRODIN MRODIN+MRODOUT MRODIN+MRODOUT+ROBIN 5 October nd ATLAS ROD Workshop 23

24 MROD Performance Study Results CSMSIM MROD MRODIN MRODOUT ROBIN ROBSIM MRODIN (2x) + MRODOUT + ROBIN, 6 TDCs Event rate [khz] Words/TDC MRODIN MRODIN+MRODOUT MRODIN+MRODOUT+ROBIN 5 October nd ATLAS ROD Workshop 24

25 MROD Performance Study Results CSMSIM MROD MRODIN MRODOUT ROBIN ROBSIM MRODIN (3x) + MRODOUT + ROBIN, 6 TDCs Event rate [khz] Words/TDC MRODIN MRODIN+MRODOUT MRODIN+MRODOUT+ROBIN 5 October nd ATLAS ROD Workshop 25

26 MROD Performance Analysis Measured event rate for single output 40 MHz with 3 input channels: event rate min(50,1000/(10 + #words-per-csm/6) khz. MROD-1 uses 80 MHz: both processing speed and bandwidth increase proportionately event rate 100 khz? Final MROD: 100 MHz. 5 October nd ATLAS ROD Workshop 26

27 FE parameter loading/initialization TTC MDT-DAQ TDCs ASDs CSM MROD ROB Mezzanine boards DCS JTAG routing: 5 October nd ATLAS ROD Workshop 27

28 JTAG Usage Initialize/Set/Reset ASD/TDC/CSM parameters Reload CSM Flash Memory (if/when needed) Calibration sequence: 1: JTAG enables calibration pulses in the ASD 2: TTC signals the CSM to send a test pulse 3: TTC provides calibration trigger No calibration during regular data taking. 5 October nd ATLAS ROD Workshop 28

29 MROD Names (NIKHEF and Univ.of Nijmegen) Henk Boterenbrood Peter Jansweijer Gerard Kieft Adriaan König Jos Vermeulen Thei Wijnen NN (Post-doc vacancy at Univ.of Nijmegen: 5 October nd ATLAS ROD Workshop 29