Coupling the AGATA Demonstrator to other detectors: the AGAVA GTS interface

Transcription

1 Electronics and interfacing do DAQ Coupling the AGATA Demonstrator to other detectors: the AGAVA GTS interface Piotr Bednarczyk Instytut Fizyki Jądrowej im. Henryka Niewodniczańskiego Polskiej Akademii Nauk

2 An ancillary detector for AGATA, a model case Fully digital, trigger-less system: detector data time-stamped and stored in a pipeline EB EB + RFD RFD example example digitizers + PSA próbkowanie impulsu,eγ 1,Eγ 2, Eγ n, GTS - Time stamp Data Merging AGATA Analogue VME {de/dx, ToF, θ, φ} rekonstrukcja przypadku Tracking RecoilFilterDetector Analogue VME electronics with a trigger, data organized in events ANCILLARY detectors: beam trackers particle, HI detectors γ-detectors interaction point outgoing particle velocity vector complementary information

3 Merging ancillaries to AGATA DAQ through AGATA TAVMEADAPTER prompt trigger <500ns Digitizer Ancillary Analogue FEE Ancillary VME DATA Req. Ancillary readout AGAVA GTS supervisor Clock counter Event Number Req. Trig- Val/Rej GTS tr. Pre-processing GTS tr. LLP PSA Event Builder Ancillary Merge USER provided: Tracking Slow control: Kmax, Labview, Midas, etc. VME processor, DSP software NARVAL producer: filtering, kinematics reconstr. Data analysis

4 AGAVA- the block diagram Standard VME module (slave) compatible with VXI A carrier for the GTS mezzanine card Delivers path for signals from/to the GTS mezzanine and the VME P1, P2 connectors Delivers 10W 3.3 V to the GTS module Delivers the Ethernet link to the GTS module Interface to the Metronome unit and the Shark-Link module (TDR JYFL)

5 GTS Trigger request and validation timing diagram AGAVA respects the GTS protocol: requests internal (test) external from FEE 1μs 6μs receives busy Data ready active till the next trigger request can be accepted by AGAVA VME readout

6 AGAVA operating modes IMPLEMENTED : SLOW -Standard VME access -CBLT VME; LNL, (GSI?) -CBLT VXI; GANIL FORESEEN: FAST parallel TDR; JYFL, Special attention: Chained BLock Transfer efficient method to read sparse data A A master CPU addresses several slaves at once The slaves determine who is to drive the data bus in response to a data strobe by passing a token via a daisy chain

7 The slow operation mode successfully tested in the LNL-VME and GANIL-VXI environments time-out if no Val/Rej Trigger req. Local Trigger Validation Trigger Data ready

8 The fast operation mode Idea: Do not wait for the whole Loc_Trig-Val./Rej Val./Rej.. sequence Read out the two Tags independently Synchronize and filter data stored in a memory

9 Connection to TDR Idea: insert the AGATA timestamp into the TDR data stream The TDR data acquisition and Software Event builder will treat the GTS timestamp data items in the same way as TDR ADC data items. Proposed by P.J.Coleman-Smith TDR Hardware prepared, but not tested

10 AGAVA registers Address (hex) Inhalt Type CBLT Status Control Register bits 0 1 R/W Agava Status Register R/W C CBLT Address Register bits 0 7 R/W Local Trigger Counter R/clr CBLT Header R/W Validation Trigger Counter R/clr CBLT Trailer R/W 00800C Rejection Trigger Counter R/clr Trigger Input Counter R/clr Local Tag bits R 00804C Timeout Counter R/clr Local Tag bits R Fast Clear Delay R/W Validation Tag bits R BC VXI related R/W C Validation Tag bits R 0080B0) Inspection Lines Control Register R/W C Event Number bits R Rejection Tag bits R Rejection Tag bits R LLP Status bits 0 7 R/W GTS Status bits 0-7 R MSG IN bits 0-7 R/ Status Reg. GTS related CBLT related VXI related inspection line spare The block control: -operation mode -trig. type -clear flags

11 The AGAVA front panel Ethernet link to GST mezzanine connectors to TDR GTS optical clock lines control LEDs: DATA-ready, Val., Rej., busy, Loc_Trig. Input signals: back pressure, Trig. request fixed inspection lines: Loc_trig., Rej., Val. busy, timeout programmable inspection lines

12 AGAVA production status 10 boards electronically assembled (ordered from: LNL, Milan, GANIL) corresponding GTS mezzanine boards are not available ongoing quality tests front panel finishing manual under preparation a first complete board will be available for collaborators very soon

13 PRISMA with AGATA DAQ scheme PRISMA E.Calore SETUP + CONTROL A C A G P D A U C V A Pre-preccessing & Narval Producer VME CBLT Event rate: ~20kHz (5Mb/sek) GTS... Narval Narval Narval

14 The AGAVA interface history Specification: AGATA Ancillary Detectors and Ancillary Detector Integration Working Group Specifications of the AGAVA (AGata Ancillary Vme Adapter) Ancillary Detector GTS Interface Work Document Version 1.2, July 2005 Contributors: D. Bazzacco, P. Bednarczyk, M. Bellato, P.J. Coleman-Smith, A. Czermak, B. Dulny, A. Gadea, Ch. Houarner, R. Isocrate, P. Jones, W. Meczyński, L. Olivier, V. Pucknell, Ch. Theisen, Ch. Weber, G. Wittwer, M. Ziębliński. Design and production: B.Dulny, A.Czermak, W.Męczyński, B.Sowicki, M.Ziębliński IFJ-PAN Kraków Tests (Kraków, LNL, GANIL): B.Dulny,J.Grębosz, IFJ-PAN Kraków, S.Brambilla, INFN-Milano F. Saillant, G. Wittwer GANIL

15 At work with AGAVA