Gerard J. Oxoby. Stanford Linear Accelerator Center Stanford University, Stanford, CA INTRODUCTION

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1 SLAC-TN-80-5 November 1980 IBM CHANNEL TO PDPll INTERFACE' Gerard J. Oxoby Stanford Linear Accelerator Center Stanford University, Stanford, CA INTRODUCTION An interface between a UNIBUS and a I/O Channel of the IBM 360/ 370 computer triplex at SLAC has been designed by experimental Group B (1 and 2). IBM calls such a device a "Control Unit" (CU) and it looks like a tape or a disk drive to the IBM computer. This means that any ordinary batch jobs can transfer data to or from a device connected to a UNIBUS. The programmer gets access to the system by a FORTRAN callable subroutine. This control unit permits bidirectional data transfers at up to lmb/sec. between an IBM 2860 Selector Channel and any DEC PDPll minicomputer peripheral conforming to IBM GA and DEC PDPll UNIBUS interfacing specifications. Appendix A is a description of the simulator developed to debug this control unit without using one of the IBM computers. SPECIFICATIONS This control unit permits bidirectional data transfers between an IBM 2860 selector channel and a PDPll minicomputer. The IBM machine controls the direction of the data transfers. The UNIBUS interface uses the direct memory access feature (DMA).,k Work supported by the Department of Energy under contract number DE-AC03-76SF00515.

2 -2- Selection by the channel and status generation are handled entirely by the hardware. A power control chassis is implemented for Emergency Power Off (EPO) in accordance with IBM specifications GA It also houses the relays for power switching and time-delay relays for the Select-Out Tag Line Bypass. To simplify manual intervention the PDPll console has been modified so that a single three position switch controls POWER OFF, OFF LINE and ON LINE. Actual change from OFF LINE to ON LINE, or vice versa occurs only when the control unit conditions permit it. With the system OFF LINE the PDPll can be controlled by the INIT/ BOOT and HALT/RUN switches. When ON LINE the INIT and BOOT are controlled respectively by an IBM system reset and a BOOT command from the channel, the switches are in this case disabled. The firmware of the M9301 bootstrap terminator was modified to jump in the console emulator in the OFF LINE mode or prepare the interface for a data transfer when ON LINE. IBM INTERFACE 1. Addresses This control unit can recognize any two consecutive IBM addresses. The lower order one is used for booting the PDPll and initial program loading (IPL) the other one for normal data transfers. 2. Commands The IBM commands accepted are as follows: PO TEST I/O 1xxxx0000 SENSE Pxxxxoloo WRITE Pxxxxoool READ Pxxxx0010 BOOT then WRITE Pxxxoooll BOOT then READ Pxxxlooll X = Don't care

3 -3-3. Status The status generated to the channel by the hardware may be any of the following: P 0 PARITY 2 3 BUSY 4 CHANNEL END 5 DEVICE END 6 UNIT CHECK 7 UNIT EXCEPTION a> Initial Status The initial status presented is normally zero if the DMA is ready and no error occurred during the selection sequence. If the DMA is not ready, the word counter not loaded, a BUSY status is presented. b) End Status After a normal data transfer CHANNEL END and DEVICE END are presented. If the PDPll signals that its buffer is full UNIT EXCEPTION is also sent to the channel. It is followed by a control unit initiated selection sequence and DEVICE END status presentation when the word count is reloaded. c> Special Status UNIT CHECK is presented when the control unit detects an unusual condition that is detailed by the information available to a sense command.

4 -4-4. Sense The available sense byte is as follows: 0 Command reject 1 2 Bus out check PDP Interrupt time out a> Command Reject indicates that a command the control unit is not designed to execute was received. b) Bus Out Check indicates that the control unit detected a parity error in a received data byte or the command byte. c> Equipment Check is generated when the internal sequencer stays idle for over a fixed time (25 us.). d) Time Out is caused when the PDPll does not service the interrupt by loading the word counter or setting the buffer full bit within 100 ms. PDPll INTERFACE The PDPll has four registers shown below. Their addresses are jumper selectable but must be consecutives. COMMAND REGISTER 76XxX

5 STATUS REGISTER 76XxX Memory Address 76XxX4 Register: 15 MSB Word Count Register: 76XXX6 16 Bits, 2's complement I. COMMAND REGISTER The bits are defined as follows: 15 - STOP: When set, this bit indicates that a data transfer has been terminated by the channel whose byte count exhausted. It is reset by the start of a new transfer. 14 HALT I/O: A Halt I/O instruction has been executed by the IBM machine causing termination of the past operation. A new selection by the channel resets this bit. 13 CHAINED: A chain command was issued by the channel to indi- cate that a new selection will follow imediately. 12 STACKED: The channel did not accept the status presented by the control unit. This bit is reset after acceptance due to either a poll or selection by the channel COMMANDS: Indicate the last command issued by the channel to the control unit. A null operation (all four bits reset)

6 -6- indicates either a boot PDP command or an invalid command (see command reject sense in status register). A write command indicates write to Unibus from channel. Vice versa a read command means a data transfer from Unibus to the channel. A test I/O or Sense command does not affect the PDPll bus, they are control unit only commands. 7 INTERRUPT PENDING: This bit is set by the termination of a transfer caused by either: the channel byte count exhausted, the DMA word count overflowing, a Halt I/O instruction or a selective reset by the channel. It is reset at the end of the interrupt sequence, INIT when OFF LINE oranibm system reset when ON LINE. 6 INTERRUPT ENABLE: Set by the PDPll program, causes an interrupt when bit seven is set. Reset by program, INIT when OFF LINE or an IBM system reset when ON LINE. 5 BUFFER FULL: Set by the program, this bit indicates that no data can be accepted until the DM! is made expressively ready by loading the word count, at which time the buffer full bit is reset. It is also reset by the program, INIT when OFF LINE or an IBM system reset when ON LINE. 4 NOT USED 3 PDP BOOTED: Set by the program, it indicates that the PDPll was successfully booted by a Boot Command from the channel when ON LINE. Reset by INIT when OFF LINE or an IBM system reset when ON LINE. 2 PDP IPLED: Set by the program it, in effect, enables one of the two ports from the channel to the control unit. The other port being always enabled. This bit is reset by INIT when OFF LINE, an IBM system reset or a Boot Command. 1-o NOT USED

7 STATUS REGISTER The bits are defined as follows: 15 - ERROR: This is an error summary. This bit is set by a Selective reset from the channel or a unit check status at the control unit NOT USED 11-7 STATUS BITS: Reflect the last status accepted by the channel. Unit Exception status is caused by the setting of bit five (Buffer full in the control register) and is reset when accepted by the channel. The next status to be presented contains the Busy status bit until the DMA is made ready. Device End and Channel End are generally presented together exce'pt when a Busy status followed a Unit Exception status and the DMA is made ready. In this case Device End is presented alone. Unit Check status is a summary of the error bits in the sense information. 6 OFF LINE: Indicates that the control unit is in the OFF LINE mode. 5 CMD MODIFIER: Corresponds to bit three of the command received from the channel. 5 NOT USED SELECTIVE RESET: Set when the channel issued a selective

8 -8- reset to the control unit as a result of a malfunction detected at the channel. This condition does not clear any status or handshaking bits but merely gates off all signals to the channel. It can only be cleared by an INIT in the OFF LINE mode or an IBM system reset when ON LINE. EQUIPMENT CHECK SENSE: This bit is set whenever the internal "Watch-dog-timer" detects that the hardware is hanging in a sequence not controlled by the software. TIME OUT SENSE: The setting of this bit is caused by an over delay in setting either the Buffer full bit in the control register or loading the word count register after a request for interrupt (bit seven of the control register being set). COMMAND REJECT SENSE: Indicates that the control unit detected an invalid command, from the channel, such as "Read backward." PARITY ERROR SENSE: The control unit detected a parity error while receiving a command or data from the channel. III. MEMORY ADDRESS REGISTER This register is loaded with the first memory location to or from where the data must be transferred from or to the channel. register. It is incremented by two after each transfer. Write only IV. WORD COUNT REGISTER Loaded with the two's complement of the number of words to be transferred via the control unit.

9 -9- It is incremented after each word transfer and returns to a zero value when reaching the overflow.

10 -lo- REFERENCES 1. Paul F. Kunz et al., Experience Using the 168/E Microprocessor for Offline Analysis, Proceeding of the 1979 IEEE Nuclear Science Symposium (Feb. 1980), also SIX-PUB-2418 (Oct. 1979). 2. Gerard J. Oxoby et al, The Bermuda Triangle, SLAC-PUB-79-7 (Dec. 1979).

11 APPENDIX A IBM CHANNEL SIMULATOR This unit has been designed to troubleshoot or debug control units normally attached to an IBM channel. Under a PDPll program control it generates the handshaking and data transfers. It has two addresses. A read and write register is used to generate the simulation of the Bus out and Tag out lines. A read only address corresponds to the Bus in and Tag in lines. READ/WRITE ADDRESS Parity is generated by hardware, however, bit seven provides a means to select even parity for error checking. When this bit is reset,odd parity is sent to the control unit. This register is reset by INIT. READ ONLY ADDRESS

Input / Output. School of Computer Science G51CSA

Input / Output. School of Computer Science G51CSA Input / Output 1 Overview J I/O module is the third key element of a computer system. (others are CPU and Memory) J All computer systems must have efficient means to receive input and deliver output J