DPhy Tx card Rev 1.1 February 1, 2012

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1 DPhy Tx card Rev 1.1 February 1, 2012

2 Introduction: The DPhyTx card is an implementation of a MIPI DPhy Transmit interface. It is designed to connect to a MIPI bus slave (like a display) via SMAs and a host FPGA via the HAPS interface (Synopsis). All the MIPI protocol intelligence is supplied by the host FPGA. The card also supports BTA transactions in that once the FPGA host commands a BTA, the card can receive data supplied by the MIPI slave back to the FPGA host. The card has an additional MIPI clock out so that a user can use it as either a 4 lanes and a clock for one link or 2 lanes and a clock (times 2) to form 2 MIPI links. Both links must run at exactly the same clock rate. The card draws power from either the SATA interface or the two pin interface provided. In either case the power is +5Vdc at just over 3 amps. The card gets quite warm in normal operation as it consumes about 16 watts. The card was tested with with a test system from The Moving Pixel Company. If the user does not wish to write the interface FPGA code, it can be purchased from Northwest Logic ( An adapter is available that adapts this HAPS card to an FMC format. Also, note that the HAPS connector orientation is 180 degrees opposite from conventional HAPS daughtercards. This allows the card to be used offthe-edge of the HAPS motherboard. This card consumes almost the entire 2x2 HAPS footprint but still conforms to FMC requirements. This datasheet grew out of a custom product as others have shown interest in it. We plan to add the necessary design details as users request and require them. Feel free to contact Scott Silver, scott.silver@movingpixel.com for more information.

3 Signals on HAPS interface: Outputs from card to host: MPClk[7..0] Differential SSTL1-2.5 One pair per data byte (MPD[]). Clocks data out of the host to the card. All 4 of these clocks will be exactly the same. LPPData[7..0] CMOS 2.5V Low speed parallel data recovered from BTA transaction with slave on lane 0. LPPStb CMOS 2.5V Rising edge strobe LPPData[] into host. LPPDAux[7..0] CMOS 2.5V Low speed parallel data recovered from BTA transaction with slave on lane 2. LPPAuxStb CMOS 2.5V Rising edge strobe LPPDAux[] into host. LP0pIn, LP0nIn CMOS 2.5V LP lane 0 signals seen on the interface. Used to recover BTA transaction data with slave. Can be used instead of LPPData[] above. LP2pIn, LP2nIn CMOS 2.5V LP lane 0 signals seen on the interface. Used to recover BTA transaction data with slave. Can be used instead of LPPDAux[] above. CD[7..0] CMOS 2.5V Collision Comparitors for lane 0, lane 2. CD0 goes true (high) when the LP0p signal is higher than 0.3 volts. CD1 goes true when the LP0p signal is lower than 0.9 volts. CD2 goes true when the LP0n signal is higher than 0.3 volts. CD3 goes true when the LP0n signal is lower than 0.9 volts. CD4 goes true when the LP2p signal is higher than 0.3 volts. CD5 goes true when the LP2p signal is lower than 0.9 volts. CD6 goes true when the LP2n signal is higher than 0.3 volts. CD7 goes true when the LP2n signal is lower than 0.9 volts. See the section in the document below entitled Collision Comparators for more information. ECLResetFB CMOS 2.5V Indicates the actual state of reset on the board so the host can determine if the Reset command has been accepted before removing the Reset command.

4 Inputs from host to card TxRefClk SSTL1-2.5 This clock is between 10 and 20 MHz. It is the reference clock for the PLL. The user adjusts the frequency of this clock to achieve fine adjustment of the output clock (and hence bitrate). Reset SSTL-1 2.5V This signal resets the output muxes to the same state. TxRefClk should be stable before releasing reset. The card should be reset anytime the clock frequency is changed. Reset need not be applied during delay line configuration. Be aware that when reset is active, the card will not generate MPClk[]. MPD[31..0] SSTL-1 2.5V MIPI high speed parallel data. Lane 0 data is MPD[7..0]. Lane 1 data is MPD[15..8] and so on. The low bit of each byte is shifted out first. For example, for lane 0, the first bit shifted out is MPD[0]. LPD[7..0] CMOS 2.5V Low power data signal for each MIPI lane. LPD[0] is MIPI Data Lane 0p signal, LPD[1] is MIPI Data Lane signal 0n, and so on. HSDisable[5..0] CMOS 2.5V Disables the HS data differential drivers. One for each lane and one for each clock output. LSDisable[5..0] CMOS 2.5V Disables the LP data drivers. One for each lane and one for each clock lane. ClkZeroPri CMOS 2.5V Forces the HS Clock being output to zero. Usually used when transitioning from LP mode to HS mode. Hold active until you wish HS Clock to be a clock signal and not a high speed logic zero. Affects the primary MIPI output clock. ClkZeroSec CMOS 2.5V Forces the HS Clock being output to zero. Usually used when transitioning from LP mode to HS mode. Hold active until you wish HS Clock to be a clock signal and not a high speed logic zero. Affects the secondary MIPI output clock. HSLoad, HSClk, HSData CMOS 2.5V Low speed serial data and clock for setting up the PLL and the delay line. All serial data should be loaded prior to reset. Data is accepted on rising edge of the clock. HSLoad should be low until the shift of new data is complete. Then it should be pulsed high then back low. Max data rate for PLL is 10 MHz. PLL chain is 12 bits. Starting from the last bit clocked in to the first bit clocked in: 7 bits divider value, 2 bits post divider, 3 bits test mode. Test mode bits should be set to 000b. Post divider is set as follows: 00b = /2, 01b = /4, 10b =/8, 11b = /1. Delay line is 20 bits (2 x 10 bits, it is a dual delay line). It is at the beginning of the chain so its data must be transmitted last. The delay line used is the SY89297, delay line A only. LSB must be transmitted first. Value is linear in delay in approx. 5pS steps. Value clocked into section B is don t care. No practical limit on shift clock frequency. ClkLPD[3..0] CMOS 2.5V Low power data for clock lanes. Other interfaces: SATA for power: standard 22 pin connector. Will use 5V only. 12x SMAs for MIPI outputs: Lane 0p, Lane 0n, Lane1p, Lane1n, Lane2p, Data 2n, Data3p, Data3n, PriClkp, PriClkn, SecClkp, SecClkn 2x I2C passthrough connections 8 test points with active low LEDs.

5 Usage Notes: Setting the output frequency/output bit rate TxRefClk should be set as follows to generate the indicated output clock. The output clock is at half the desired bitrate. For example, if the output clock is set to 500 MHz, the resulting output bit rate per lane is 1000Mbps. Range 1: 800 MHz 1600 Mbps 20 MHz (divider set to 40, post divider set to 1) 400 MHz 800 Mbps 20 MHz (divider set to 20, post divider set to 1) Note that any frequency on 20 MHz boundary between 400 and 800 MHz can be set by changing the divider between 20 and 40. To get a frequency at a finer granularity, set the divider to the next highest frequency and lower the reference. For example, if 803 Mbps is desired (401.5 MHz), one would set the divider to 21 (with a 20 MHz reference, would generate 420 MHz) and lower the reference to MHz. 1583Mbps (791.5 MHz) set divider to 40 and lower the reference to MHz. To get lower ranges, set the post divider to higher values. Divide by Mbps-> 400 Mbps Divide by Mbps-> 200 Mbps Divide by Mbps->100 Mbps By the standard, the lowest valid MIPI HS clock frequency is 80 MHz (160 Mbps). However, as indicated above, the card can go as low as 50 MHz (100 Mbps). Also note that there is not one unique set of settings for each frequency; one can pick many reference/divider combinations to achieve most output frequencies. Those at the end of the range are unique. The PLL device we are using is the On Semi NBC12439A. It has a minimum divider setting of 20 and a maximum of 80. It can be set outside this range but that will be operating the device out of it specified range. The reference can be set as low as 10 MHz or as high as 100 MHz. We recommend operation around 20 MHz for best performance. Calibration values and delay line setting To generate the clock and data in a quadrature relationship, this card uses a delay line to delay the clock into the correct position. Ideally, assuming a natural output of the clock and the high speed data being simultaneous, the delay line would be set to exactly ¼ HS clock cycle time. However, the output relationship between the clock and the data is not ideal, the delay line does not have 0 delay at 0 setting, and the delay line delay gain variation from part to part is significant. The card is supplied with a delay offset value and a delay gain value. With these two values, a user can set the delay line to achieve quadrature at any desired output frequency. The delay line has a ~5 ns range, enough to get to quadrature for frequencies as low as 50 MHz. The delay line we are using is a Micrel SY Note that the inherent minimum delay through the delay line is much more than one clock cycle at the highest speeds. This requires that the user adjust the delay line more than 360 degrees of the clock (in most cases) to get to quadrature timing. Data interface: We recommend that the user take in the MPClk signal and regenerate it via a PLL to clock the data from the host to the card. This allows the user to maintain very tight (and compile-time adjustable) timing between the host and the card. The disadvantage of this approach is that 1) a PLL is required, 2) the clock from the card to the host must be continuous in time so as to keep the PLL locked. As long as Reset signal is not asserted to the card, the card will generate a continuous-time MPClk signal to the host. We recommend that reset be applied only once at the beginning of operation and not again during normal operation. The device that the data is feeding is an ON Semi MC10EP446 serializer. The setup and hold times can be found in the datasheet. Note that the setup time is negative! Remember the timing is from the clock coming from this device, travelling to the FPGA, clocking the data from the fpga, then the data travelling back to the device. Since we don t know exactly what the flight times are, we will need to calibrate this and work this into the FPGA

6 PLL/delay settings at initial design turn-on. It will become a static value to be fed back into the FPGA compile onetime. BTA: during a BTA, the user should turn off both the high speed drive and the low power drive to lane 0. By having completely independent HS Enable and LP Disable controls, we do not need a separate BTA enable. LP-HS Timing: The serializers have inherent delay. This delay is 2 MPClk cycles; that is to say that data transmitted by the host to the card on one edge of the MPClk will appear at the output of the card two rising edges of the PClk later. Applications may wish to delay LP signal timing to better align with the HS serial data as the delay for the LP signals is quite small. Collision comparators (for collision detection): 8 signals are provided from the card to the host. In order to detect collisions, one needs both the information of the desired state of the signal and the actual state of the signal. Two collision comparators are provided for each of the 4 signals that the user may wish to monitor. To detect a collision: IF LPD[0] is High AND CD[1] is High (connection is lower than 0.9 volts) THEN there is a collision. LPD[0] never got high as commanded. IF LPD[0] is Low AND CD[0] is High (connection is higher than 0.3 volts) THEN there is a collision. LPD[0] never got low as commanded.

7 General description of operation: Drive Reset inactive. Via serial bus, set the PLL and delay lines. Wait 100 ms. Drive Reset active for at least two MPClk periods. Set all lanes for LP11. Set LPDisable[] all low (inactive, meaning LP is being output). Set HSDisable[] all high (active, meaning no HS output) Set ClkZeroPri and ClkZeroSec active. Set all zeros being driven into the serializers (MPD[] = all zeros.) Drive reset inactive. Start generating traffic. For the clock, go through the proper clock start protocol. It will look like: LP11 LP01 LP00 LPDisable[5..4] = all high (turn off LP drivers) HSEnable[5..4] = all low (turn on HS drivers) Set ClkZeroPri (and Sec if so desired) to 0 after the required wait time. This allows the clock to be transmitted. Normal data traffic control for a given lane would be: LP11 LP01 LP00 LPDisable[3..0] = all high. HSDisable[3..0] = all low. Send HS data through the MPD[] bus. If you are going to stop the clock, now go through the proper clock stop protocol.

8 Specifications and Mechanical details Max output data rate 1.2 Gbps/lane Power consumption: about 16 watts Board Dimensions: 140mm long x 70mm wide.

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