MAX 10 - ADC. Last updated 8/12/18

Transcription

1 MAX 10 - Last updated 8/12/18

2 A/D Analog to Digital Conversion Most of the real world is analog temperature, pressure, voltage, current, To work with these values in a computer we must convert them into digital representations Three steps to this conversion Sampling Quantizing Encoding 2 tj

3 A/D Sampling A to D Conversion takes a finite amount of time What if the input changes during this time? We must take a snapshot of the input Sample and Hold Vin Sample Vout 3 tj

4 A/D Sampling Sampling is a kind of MODULATION Modulation systems are subject to Aliasing Fin < fs/2 Frequency 0 Fs: Nyquist rate LPF the input (anti-aliasing filter) Frequency 0 fs Frequency 0 fs 4 tj

5 A/D Sampling Example of analog aliasing 5 tj

6 A/D Quantizing In the A to D process we are converting an infinite resolution analog signal into a finite number of digital bits Converters use reference voltages to set the range of allowed input voltages - Vref-H, Vref-L Each binary step represents (V ref-h V ref-l ) / 2 n for an n bit conversion e.g. 0V 1V input converted to 3 bit digital value each binary step represents 0.125V since 000 typically represents 0.0V, 111 represents 0.875V 6 tj

7 A/D Quantizing Quantization error looks like noise on the signal (Quantization Noise) Dynamic Range is a measure of signal to noise ratio. (SNR in db) For an AtoD the Dynamic Range is the measure of signal to Quantizing Noise ratio (SQNR) SQNR = 20 log 10 (2 n /(1/2 (-1/2)) = 20 log 10 2 n 8bit 48dB 10bit 60dB n steps Step Size rel to Vref-H - Vref-L SQNR (db) tj

8 A/D A/D Conversion Example 10 bit converter with VrefH=3.0V, VrefL=0.0V If the input is 2V, what is the output code VrefH-VrefL = 3V range 10 bit converter step size = range/2 10 = mV/step 2V / mV/step = 682 steps from VrefL tj

9 A/D Successive Approximation A to D Uses an iterative process to determine the correct digital value for the analog input Requires Input (sample and held) A register to hold the current estimate of the digital value D to A converter to convert the digital estimate back to analog A comparator to determine if the estimate is above or below the actual input value Control logic to run the process Uses a binary search to find the nearest code value to the input value 9 tj

10 A/D Successive Approximation A to D Vin + _ Clk CONTROL VrefH VrefL D to A Successive Approximation Register OUTPUT LATCH Output Code 10 tj

11 A/D Successive Approximation A to D The control logic resets the SAR before each conversion The control logic then sets the msb The DtoA converts this to ½ the reference voltage The comparator tests to see if the input is above or below this value if above, the 1 in the msb stays if below, the msb is reset to zero The control logic then sets the msb-1 bit The DtoA converts this to the appropriate voltage level The comparator tests to see if the input is above or below this value if above, the 1 stays if below, the msb-1 bit is reset to 0 The control logic then sets the msb-n bit The DtoA converts this to voltage The comparator tests to see if the input is above or below this value if above, the 1 stays if below, the msb-n bit is reset to 0 Vin Clk D to A + _ CONTROL Successive Approximation Register Output Code VrefH 11 VrefL tj OUTPUT LATCH

12 Steps relative to VrefH-VrefL A/D Successive Approximation A to D Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 12 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 tj

13 Configuration 2 channels SAR type conversion 12 bit conversion 1MHz (max) operation 1 dedicated input / channel 8 programmable inputs / channel 0 2.5V conversion range 13 tj

14 Configuration 14 tj

15 Configuration 15 tj

16 Configuration Special Pre-scaler mode for Channel 8 Divides input voltage by 2 Allows input voltages up to 5V with a 2.5V reference 16 tj

17 Configuration Clocking Must use PLL for clocking PLL1 or PLL3 Voltage Reference Internal and external reference options Common external reference pin Common internal reference Can select references separately for each Temperature Sensor 1 has an on-die temperature sensor 17 tj

18 Configuration 2 IP Cores Altera Modular IP core Can be use either Both cores can be used at the same time If both cores used they will operate asnychronously Altera Modular Dual IP core Instantiates both cores ANAIN1 and ANAIN2 inputs are samples synchronously All other pins are asynchronous 18 tj

19 Configuration 4 Configurations for each core Standard Sequencer with Avalon-MM Sample Storage Sequencer manages multiple input pins and sequencing of samples Samples are stored in on-chip memory (Sample Store) Control controls the process Managed by processor 19 tj

20 Configuration 4 Configurations for each core Standard Sequencer with Avalon-MM Sample Storage Dual Core Sequencer manages multiple input pins and sequencing of samples Merged samples are stored in on-chip memory (Sample Store) Control controls the process independently Managed by processor 20 tj

21 Configuration 4 Configurations for each core Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection Adds a splitter Compares values to thresholds and provides a violation signal 21 tj

22 Configuration 4 Configurations for each core Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection Dual Core Adds a splitter Compares values to thresholds and provides a violation signal 22 tj

23 Configuration 4 Configurations for each core Standard Sequencer with External Sample Storage Sequencer manages multiple input pins and sequencing of samples Control controls the process Managed by processor Samples are stored outside the IP core 23 tj

24 Configuration 4 Configurations for each core Standard Sequencer with External Sample Storage Dual Core 24 tj

25 Configuration 4 Configurations for each core Control Core Only Control controls the process Managed by processor No Sequencer Samples are stored outside the IP core 25 tj

26 Configuration 4 Configurations for each core Control Core Only Dual Core 26 tj

27 Configuration Configuration Blocks 27 tj

28 Configuration Configuration Blocks 28 tj

29 Core 29 tj

30 Core 30 tj

31 Core 31 tj

32 Core 32 tj

33 Configuration 3 approaches to using the s Used with the Quartus ToolKit (Inside System Console) to verify operation Avalon interface built into the toolkit Used as part of a NIOS system Avalon interface built in by Platform Designer Used with a hand built interface Emulate the Avalon interface 33 tj

34 Example using Toolkit Module Configuration Enabled for the Toolkit Only 1 available on DE10-Lite Max Sample Rate Required Clock Channel 1 Arduino A0 pin Sequencer Setup 34 tj

35 Example using Toolkit Platform Planner Clk driver required for PLL 10MHz PLL output Block Debug interface for Toolkit Toolkit controls the Avalon Interface through this module 35 tj

36 Example using Toolkit DE10 top level design adc_basic_de10.vhdl by: johnsontimoj created: 6/28/ version: example - de10 implementation inputs: CLK, in 1 (via IP) outputs: none Use System Console - Toolkit for validation library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adc_basic_de10 is port ( CLOCK_50: in std_logic ); end entity; architecture toplevel of adc_basic_de10 is component adc_basic is port ( clk_clk : in std_logic := 'X'; -- clk begin reset_reset_n : in std_logic := 'X' -- reset_n ); end component adc_basic; u0 : component adc_basic port map ( clk_clk => CLOCK_50, -- clk.clk reset_reset_n => '1' -- reset.reset_n ); -- no activity end architecture; 36 tj

37 Example using Toolkit Setup Analog Discovery Waveform Output Arduino AO pin DE10-Lite 37 tj

38 Example using Toolkit 38 tj

39 Example using Toolkit Toolkit results Looks like there is a DC offset 39 tj

40 Control Interfaces To create a logic controller 40 tj

41 DE10-Lite WARNINGS Only 1 is brought out to pins No access to 2 inputs The pin #s are shifted Arduino A0 is mapped to 1_in1 Arduino A5 is mapped to 1_in6 No other inputs are pinned out 41 tj