7. Integrated Data Converters

Transcription

1 Intro Flash SAR Integrating Delta-Sigma /43 7. Integrated Data Converters Francesc Serra Graells Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated Circuits and Systems IMB-CNM(CSIC)

2 Intro Flash SAR Integrating Delta-Sigma 2/43 ADC vs DAC 2 Flash Architectures 3 SAR Topologies 4 Integrating Solutions 5 Delta-Sigma Modulators

3 Intro Flash SAR Integrating Delta-Sigma 3/43 ADC vs DAC 2 Flash Architectures 3 SAR Topologies 4 Integrating Solutions 5 Delta-Sigma Modulators

4 Intro Flash SAR Integrating Delta-Sigma 4/43 ADC vs DAC General mixed-mode frontend for smart transductors: sensor e.g. microphone pre amp AGC/ limiter anti alias ADC core decimator clock generator DSP M DAC core interpolator actuator e.g. motor power amp reconstruction

5 Intro Flash SAR Integrating Delta-Sigma 5/43 ADC vs DAC General mixed-mode frontend for smart transductors: sensor e.g. microphone pre amp AGC/ limiter anti alias ADC core decimator information action clock generator DSP M DAC core interpolator actuator e.g. motor power amp reconstruction...typically ADC is more performance demanding!

6 Intro Flash SAR Integrating Delta-Sigma 6/43 ADC Families Classification based on architecture approach: Flash High speed Sub-ranging Analog signal Digital signal Parallel Interleaved ADC Pipeline voltage/current amplitude Digital timebase code Algorithmic Predictive SAR Integrating Delta-Sigma Distinctive characteristics: Feedforward vs feedback control Single vs multiple stages Amplitude vs time domains...and many more! Typically mixed solutions... High dynamic range

7 Intro Flash SAR Integrating Delta-Sigma 7/43 ADC Evolution EPSCO DATRAC, B.M. Gordon, 953 -bit 50KSps 500W SAR ADC 0.5m x 0.4m x 0.65m, 70Kg Vacuum tube technology W. Kester, Analog-Digital Conversion archives/39-06/data_conversion_handbook.html

8 Intro Flash SAR Integrating Delta-Sigma 8/43 ADC Evolution +60years Flash Pipeline SAR Delta-Sigma Other State-of-art ADC Solid-state technologies B. Murmann, ADC Performance Survey EPSCO DATRAC, B.M. Gordon, 953 -bit 50KSps 500W SAR ADC 0.5m x 0.4m x 0.65m, 70Kg Vacuum tube technology W. Kester, Analog-Digital Conversion archives/39-06/data_conversion_handbook.html P/f s [J] fJ/conv-step 70dB SNDR [db] -bit

9 Intro Flash SAR Integrating Delta-Sigma 9/43 ADC Evolution ADC Performance enhancement: Architecture strategy Circuit design Integration technology State-of-art ADC Solid-state technologies Still room for further improvement? Flash Pipeline SAR Delta-Sigma Other B. Murmann, ADC Performance Survey P/f s [J] SNDR [db]

10 Intro Flash SAR Integrating Delta-Sigma 0/43 ADC vs DAC 2 Flash Architectures 3 SAR Topologies 4 Integrating Solutions 5 Delta-Sigma Modulators

11 Intro Flash SAR Integrating Delta-Sigma /43 Basic Flash Architecture ADC Building blocks: e.g. single-ended 3-bit flash ADC Threshold generator Latched comparator array thermometer code Digital encoder natural binary code combinational only logic

12 Intro Flash SAR Integrating Delta-Sigma 2/43 Basic Flash Architecture ADC Building blocks: e.g. single-ended 3-bit flash ADC Threshold generator Latched comparator array thermometer code clock cycle conversion time natural binary code Digital encoder Area and power scaling by 2 ENOB Distortion due to technology mismatching combinational only logic

13 Intro Flash SAR Integrating Delta-Sigma 3/43 Latched Comparator Design Compact CMOS circuit: Non-overlapped clock phases clock M3 M4 M M2

14 Intro Flash SAR Integrating Delta-Sigma 4/43 Latched Comparator Design Compact CMOS circuit: clock M3 M4 High-speed operation Non-overlapped clock phases Each comparator crosses at different threshold V thk M M2 Threshold voltage offset? Pre-charging phase Decision phase M3 M4 0 0 M3 M4 Positive feedback to speed-up comparison Symmetrical loading M M2 M M2

15 Intro Flash SAR Integrating Delta-Sigma 5/43 Comparator Optimization By attaching an array of level shifters: clock single-ended version Ck C2k signal baseline Ck C2k Ck C2k

16 Intro Flash SAR Integrating Delta-Sigma 6/43 Comparator Optimization By attaching an array of level shifters: clock Ck C2k single-ended version All comparators latch at the same level (V ref ) Single comparator design Low quiescent power (resistor-less thresholds) Capacitor area overhead Input capacitance increased Slower operation signal baseline Ck C2k Ck C2k effective signal effective k-threshold

17 Intro Flash SAR Integrating Delta-Sigma 7/43 Comparator Optimization By attaching an array of level shifters: clock Ckp C2kp fully-differential version Interference rejection Full-scale extension (+6dB) SNR enhancement (+3dB) Distortion cancellation (even harmonics) Ckn C2kn Area and power overheads (x2) Higher symmetry requirements Time

18 Intro Flash SAR Integrating Delta-Sigma 8/43 Comparators Offset Distortion due to DNL MOSFET V TH mismatching effects: M3 M4 M M2 CMOS technology Pelgrom's Law

19 Intro Flash SAR Integrating Delta-Sigma 9/43 Comparators Offset Thermometer code bubbles! Error propagation at encoding... Bubble 0 0 Latched comparator array 0 Digital encoder Gaussian probability distribution Large device area (WL) and input capacitance penalties

20 Intro Flash SAR Integrating Delta-Sigma 20/43 Comparators Offset Thermometer code bubbles! Digitally assisted analog design: Latched comparator array Bubble Bubble error correction (BEC) Digital encoder?

21 Intro Flash SAR Integrating Delta-Sigma 2/43 Comparators Offset Thermometer code bubbles! Digitally assisted analog design: Latched comparator array Bubble Bubble error correction (BEC) Digital encoder (WL) large enough to limit bubble distance to code: 0 X X 0 X 0 X

22 Intro Flash SAR Integrating Delta-Sigma 22/43 Comparators Offset More on digitally assisted analog design: an stochastic flash ADC Digital inverse Gaussian integral e.g. 63 comparators Digital full-adders S. Weaver, B. Hershberg and Un-Ku Moon, Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells, IEEE Transactions on Circuits and Systems I, 6():84-9, Jan 204

23 Intro Flash SAR Integrating Delta-Sigma 23/43 Comparators Offset More on digitally assisted analog design: an stochastic flash ADC Almost digital Compact area Digital inverse Gaussian integral Non-linearity compensation required Power consumption e.g. 63 comparators Digital full-adders S. Weaver, B. Hershberg and Un-Ku Moon, Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells, IEEE Transactions on Circuits and Systems I, 6():84-9, Jan 204

24 Intro Flash SAR Integrating Delta-Sigma 24/43 ADC vs DAC 2 Flash Architectures 3 SAR Topologies 4 Integrating Solutions 5 Delta-Sigma Modulators

25 Intro Flash SAR Integrating Delta-Sigma 25/43 Successive Approximation ADC ADC Building blocks: residue S/H digital state-machine (algorithm) approximation Flash DAC N-bit Successive Approximation Register (SAR) N

26 Intro Flash SAR Integrating Delta-Sigma 26/43 Successive Approximation ADC ADC Building blocks: residue e.g. 4-bit SAR ADC S/H digital state-machine (algorithm) approximation Flash DAC N-bit Successive Approximation Register (SAR) N MSB LSB time time Analog minimalist Very low-power consumption Speed requirements (xn) Performance limited by flash DAC

27 Intro Flash SAR Integrating Delta-Sigma 27/43 Successive Approximation ADC Circuit implementation: clock S/H Flash DAC N-bit Successive Approximation Register (SAR) N single-ended version to SAR from SAR signal baseline

28 Intro Flash SAR Integrating Delta-Sigma 28/43 Successive Approximation ADC Circuit implementation: clock S/H Flash DAC N-bit Successive Approximation Register (SAR) N single-ended version to SAR from SAR signal baseline

29 Intro Flash SAR Integrating Delta-Sigma 29/43 ADC vs DAC 2 Flash Architectures 3 SAR Topologies 4 Integrating Solutions 5 Delta-Sigma Modulators

30 Intro Flash SAR Integrating Delta-Sigma 30/43 Single-Slope ADC ADC Building blocks: S/H enable reset Digital counter N pulse-width modulation (PWM) clock 0 time

31 Intro Flash SAR Integrating Delta-Sigma 3/43 Single-Slope ADC Building blocks: S/H enable reset Digital counter N pulse-width modulation (PWM) clock Analog minimalist Very low-power Speed requirements (x2 N ) Technological sensitivity (RC) 0 time

32 Intro Flash SAR Integrating Delta-Sigma 32/43 Dual-Slope ADC ADC Building blocks: S/H control reset Dual counter N clock Analog minimalist Very low-power Speed requirements (x2 N ) Technology independence (RC) 0 time

33 Intro Flash SAR Integrating Delta-Sigma 33/43 Integrate-and-Fire ADC ADC Building blocks: reset Asynchronous counter N pulse-density modulation (PDM) Current-mode sensors (e.g. imagers) Very low-power Speed requirements adapted to signal Technology sensitivity (C) 0 time

34 Intro Flash SAR Integrating Delta-Sigma 34/43 ADC vs DAC 2 Flash Architectures 3 SAR Topologies 4 Integrating Solutions 5 Delta-Sigma Modulators

35 Intro Flash SAR Integrating Delta-Sigma 35/43 Delta-Sigma Modulator ADC ADC General single-loop DSM architecture: noise-shaper (predictor) quantizer error DSM digital output S/H Flash ADC Flash DAC digital decimator (down sampler) prediction feedback DAC

36 Intro Flash SAR Integrating Delta-Sigma 36/43 Delta-Sigma Modulator ADC ADC General single-loop DSM architecture: S/H noise-shaper (predictor) quantizer error prediction Flash ADC Flash DAC feedback DAC DSM digital output digital decimator (down sampler) Noise-shaper filter: In-band high-gain Either continuous- H(s) or discrete-time H(z) Flash ADC and DAC blocks can be relaxed! DSM signal vs quantization noise behavior? signal quantization noise output

37 Intro Flash SAR Integrating Delta-Sigma 37/43 Delta-Sigma Noise Shaping Simplest architecture: first-order (N=) -bit (B=) single-loop DSM S/H integrator comparator Single-bit feedback DAC is intrinsically linear time

38 Intro Flash SAR Integrating Delta-Sigma 38/43 Delta-Sigma Noise Shaping Simplest architecture: first-order (N=) -bit (B=) single-loop DSM S/H integrator comparator Single-bit feedback DAC is intrinsically linear Oversampling is needed all-pass (delay) log(power) signal 20dB/dec out-band noise (differentiator) high-pass shaping log(frequency)

39 Intro Flash SAR Integrating Delta-Sigma 39/43 Delta-Sigma Noise Shaping Simplest architecture: first-order (N=) -bit (B=) single-loop DSM S/H integrator comparator Single-bit feedback DAC is intrinsically linear Oversampling is needed log(power) Higher order (N>) shaping to avoid signal to quantization noise correlation (harmonics) all-pass (delay) signal in-band harmonics (differentiator) high-pass shaping log(frequency)

40 Intro Flash SAR Integrating Delta-Sigma 40/43 Delta-Sigma Noise Shaping Higher-order (N) noise shaping: first integrator second integrator S/H gain coefficients Sharper noise shaping log(power) Signal to quantization noise uncorrelation (continuous spectra) 40dB/dec Possibility of loop instability for N>2 Coefficients optimization! log(frequency)

41 Intro Flash SAR Integrating Delta-Sigma 4/43 DSM ADC Design N-order B-bit single loop architecture: S/H multi-bit (B) quantization Multi-bit quantization: Resolution added to overall DR Internal full-scale reduction Feedback DAC not intrinsically linear High-order filtering: Sharper noise shaping Stability issues Ideal dynamic range: shaping order oversampling only log(power) signal (N+0.5)-bit/oct(OSR) 20N db/dec 6N db/oct direct improvement log(frequency)

42 Intro Flash SAR Integrating Delta-Sigma 42/43 DSM ADC Design Feedfoward cancellation: Internal full scale low occupancy Additional adder stage in front of quantizer S/H Resonator attenuation: Extra noise shaping at band edge Zero sensitivity to coefficient matching log(power) S/H log(frequency)

43 Intro Flash SAR Integrating Delta-Sigma 43/43 DSM SC Circuits clock S X Fully-differential 2nd-order single-bit example: input sampler reuse for DAC feedback common mode integrator initialization passive adder