Counters. Counter Types. Variations. Modulo Gray Code BCD (Decimal) Decade Ring Johnson (twisted ring) LFSR

Transcription

1 CE 1911 Counters

2 Counter Types Modulo Gray Code BC (ecimal) ecade Ring Johnson (twisted ring) LFSR Variations Asynchronous / Synchronous Up/own Loadable 2 tj

3 Modulo-n (n = a power of 2) Asynchronous Count in binary Mod-16 b0 b1 b2 bn-1 clk_in rstb 3 tj

4 Modulo-n (n = a power of 2) Synchronous Count in binary J J J b0 b1 b2 bn-1 J K K K K clk_in rstb 4 tj

5 Modulo-m (m not a power of 2) Synchronous Has m states Mod-5 Mod n counter with logic to synchronous clear the Flip Flops when last state is reached RST n ecode Logic 5 tj

6 Gray Code Synchronous Only 1 bit changes at a time > 000 N bit state machine with next state logic Mod-n counter with output logic n Output Logic Out 6 tj

7 BC Binary Coded ecimal Synchronous Outputs limited to 0-9 Mod-m counter with m = 10 Last state (9) also enables next clock to increment the next digit 7 tj

8 ecade Synchronous 10 output states Not necessary to be 0-9 n bit state machine with next state logic Mod-n counter with output logic Last state (?) also enables next clock to increment the next digit 8 tj

9 Ring Synchronous Any number of states (1 FF / state) Rotate a single 1 or single 0 around in a loop or Note no 0 state otherwise nothing to rotate Shift register with 0 tied to last bit and 1 bit set or reset SETB b0 b1 b2 clk_in rstb 9 tj

10 Johnson (twisted ring) Synchronous Any number of states (1FF / 2 states) Rotate a pattern in a loop Shift register with 0 tied to last bit b0 b1 b2 clk_in rstb 10 tj

11 LFSR (Linear Feedback Shift Register) Synchronous pseudo random pattern generator Shift register with 0 tied to feedback logic designed to create a specific pattern Feedback Logic s b0 b1 b2 clk_in rstb 11 tj

12 Up/own capability Twice as many state transitions Loadable Logic to force desired FFs into set or reset state 12 tj

13 Counter - 4 bit nbitcounter.vhdl created 2/29/17 tj rev 0 n bit up-counter example Inputs: rstb, clk Outputs: bout[n-1:0] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nbitcounter is generic( n: natural := 4 ); port ( clk : in std_logic; rstb : in std_logic; bout : out std_logic_vector(n-1 downto 0) ); end entity; architecture behavioral of nbitcounter is internal signals signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then bout_sig <= bout_sig + 1; end if; end process; Output logic bout <= std_logic_vector(bout_sig); end behavioral; 13 tj

14 Counter mod 9 mod9counter.vhdl created 3/16/17 tj rev 0 mod 9 counter example Inputs: rstb, clk Outputs: bout[n-1:0] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mod9counter is generic( n: natural := 4 ); port ( clk : in std_logic; rstb : in std_logic; bout : out std_logic_vector(n-1 downto 0) ); end entity; architecture behavioral of mod9counter is internal signals signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then if(bout_sig = 8) then bout_sig <= (others => '0'); else bout_sig <= bout_sig + 1; end if; end if; end process; Output logic bout <= std_logic_vector(bout_sig); end behavioral; 14 tj

15 Counter mod-9 15 tj

16 Counter mod 9b mod9counterb.vhdl created 3/16/17 tj rev 0 mod9 counter example B Inputs: rstb, clk Outputs: bout[n-1:0] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mod9counterb is generic( n: natural := 4 ); port ( clk : in std_logic; rstb : in std_logic; bout : out std_logic_vector(n-1 downto 0) ); end entity; architecture behavioral of mod9counterb is internal signals signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then bout_sig <= bout_sig + 1; end if; check for terminal state if(bout_sig = 9) then bout_sig <= (others => '0'); end if; end process; Output logic bout <= std_logic_vector(bout_sig); end behavioral; 16 tj

17 Counter mod-9b 17 tj

18 Tick Counter tickcounter.vhdl created 3/16/17 tj rev 0 tick counter example Inputs: rstb, clk Outputs: ticka, tickb library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tickcounter is generic( n: natural := 4 ); port ( clk : in std_logic; rstb : in std_logic; ticka : out std_logic; tickb : out std_logic ); end entity; architecture behavioral of tickcounter is internal signals - for doing math signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then bout_sig <= bout_sig + 1; if(bout_sig = 5) then ticka <= '1'; else ticka <= '0'; end if; if(bout_sig = 7) then tickb <= '1'; else tickb <= '0'; end if; end if; end process; Output logic end behavioral; increment count ticka detect (6th clk) tickb detect (8th clk) 18 tj

19 Tick Counter 19 tj