Design of a Low Power and Stable 11T SRAM cell with bit-interleaving capability

Transcription

1 Design of a Low Power and table 11T RAM cell with bit-interleaving capability hivendra Kumar harma, Bhavana P.hrivastava M.tech cholar, Assistant Professor ECE Department, MANIT Bhopal, INDIA. Abstract A low power and high stable single ended 11T RAM cell has been proposed with bit interleaving capability. A column aware scheme is used in the cell to achieve highly stable RAM cell which exhibit better performance than the previous designs. The proposed design has robust read operation and exhibits lower power consumption and better stability as compared to existing designs. This proposed 11T RAM has been compared with conventional 6T RAM cell and 9T RAM cell in term of Power consumption, Delay and Power Delay Product (PDP) at various supply voltages as 1.8V, 1.6V and 1.4V. For the stability analysis NM (tatic Noise Margin) also analyzed at the supply voltage 1.8V. The simulations of all circuits are done on Cadence Virtuoso at 180nm CMO technology and the simulation results are analyzed and verify to show that proposed design is better than the existing designs. The proposed 11T RAM shows the better performances in terms of power consumption and PDP at all the supply voltages. At 1.8V power saving by the proposed design is 73.88% and improvement in PDP is 71.53% compared to standard 6T RAM cell and significant improvement is observed at other supply voltages also. In term of stability the proposed design showing good result as compare to existing designs. Keywords RAM cell, Leakage Power, Low Power, tability, Bit-interleaving, PDP. I. INTRODUCTION Ever since the concept of miniaturization took off, Process voltage and Temperature variations have become the prominent issues because of device scaling. But in the DM (Deep ubmicron Tech) as the size of the CMO is scaling down; the leakage power is most common issue for RAM cells which are designed for a low power application. As a result the power consumption in RAM cell becomes main problem. Low power design of RAM without compromising with the speed performance becomes the main issue in the modern VLI designs. Furthermore due to scaling the circuits also faces design challenges for low power RAM designs. Because of low V th and ultra-thin gate oxide, the leakage power consumption is increased [1]. The stability of the cell during read, write mode is also affected [2]. The adoption of supply voltage scaling becomes most effective technique for energy saving since it reduces the power consumption of the circuit in significant amount [3]. But with the scaling down of devices and supply voltages, the variability of RAMs in process variation parameters and threshold voltage together with I on I off ratio increase severely and this degrades cell stability by reducing the tatic Noise Margin (NM) [9, 10]. The NM has linear dependency on the supply voltage, as the supply voltage is scaled down for power reduction the cell stability severely get affected. Hence to get ultra-low power consumption while keeping the cell stability constant becomes the main issue of RAM designs in this scenario. In this paper, a 11T RAM cell has been proposed for bit-interleaving application. ome other RAM cell with bit interleaving have been presented in [4-8] in past. The proposed design has less power consumption, high speed, improved read and write stability, read robustness at the cost of area overhead. The brief overview of this paper as follows, in section II consist of literature review discussions i.e. standard 6T RAM and existing 9T RAM cell has been discussed. ection III elaboration of the proposed work has discussed, section IV contains the simulation results and cell performance analysis discussion and section V consists of conclusion of the whole paper. II. LITERATURE REVIEW 2.1 Conventional 6T RAM Cell The Conventional 6T RAM cell has combination of six transistors in which four transistors (N3 P1 N4 P2) formed two inverters. These two inverters are back to back connected in cross coupled manner, apart from this two access NMO transistors N1 and N2 acting as pass transistors and two data storing nodes (Q and QB). These data storing nodes are accessed by the pass transistor N1 and N2 as shown in Fig.1. These back to back connected inverters forming the latch to store the bit. The access transistors are turns on by enabling Word Line (). When the Word Line () is low, access transistors are disabled and cell works in hold mode, at this mode read or write operations cannot be IN: Page 67

2 performed, at this state latch can hold bit. When the word line becomes high, access transistors N1 and N2 are enabled, and the read and write operations can be performed [14]. Data is writes at node Q through bit line and inverted data is stored at the node QB. BL BLB P3 Word line R Read BL Bit line CBL Column BL CBLB CBL bar N5 CBL BL CBLB L N1 Q N6 P1 N3 P2 N4 QB P1 P2 N2 N1 Q QB N2 R Fig.2. Existing 9T ARM cell N3 N4 Word line BL Bit line BLB Bit line bar 2.2 9T RAM cell Fig.1 Conventional 6T RAM cell To design 9T RAM cell three extra transistors N5, N6, P3 are connected. Transistor N6 is connected between data storing node Q and N1 for the data protection during read operation [11], this transistor N6 prevent the discharging of node Q because it turn off during read, write operation. Transistor (N5, P3) forms a special inverter for AND logic operation [8] to activate local word line (L). It also have other input lines i.e. bit line ( BL),world line ( ) and provide special Read word line ( R ) for read operation, bit line CBLB have a control on transistor N5 as shown in Fig. 2. This 9T RAM cell is designed for bit-interleaving application for soft error protection and this design also overcome the problem of write 1 failure which was occurring in 6T RAM cell. Also exhibit significant improvement in write ability, read robustness, reduces write and leakage power consumption, as well as proves to be better tolerance in process variation [12]. The power consumption, speed and stability of the circuit can be further improved by connecting extra circuitry which is done in the proposed 11T design. III. PROPOED DEIGN T RAM cell ingle ended 11T RAM cell for bit interleaving application has been proposed, the idea of bit interleaving originate from the differential 8T RAM cell [10]. Later the same idea is used in read disturb free 9T RAM cell [12]. The working of the proposed cell is a little bit similar to the 9T RAM cell with improved performance parameters i.e. less power consumption, high speed, less PDP and high stability at the cost of area. The proposed RAM cell consist of eleven transistors seven NMO from N1 - N7 and four PMO from P1-P4 shown in Fig. 3. Word line R Read BL Bit line CBL Column BL CBLB CBL bar R P3 N5 CBL BL CBLB L P4 N1 N2 Q N6 P1 N3 N7 P2 N4 QB Fig.3. 11T RAM cell In the proposed circuit two extra transistors P4 and N7 are connected to improve the cell performances. The transistor N7 is for reducing supply voltage and transistor P4 is work as switching transistor. The operation principle of the proposed 11T RAM cell is discussed below. IN: Page 68

3 Hold mode: In hold mode, set the word line () at pre-charge high voltage while R signal set at low voltage that leads to transistor N1 & N2 turns off to prevent the access of bit lines, CBLB is set high to turn on transistor N6 as a result data retention is afforded by the cross coupled inverter pair. Write Mode: In write operation is set at low voltage and CBL signal set to high voltage, hence as a result L signal is pre-charged to high value hence data is written through bit-line (BL) to storage nodes ( Q & QB ) through N1. Read mode: During read mode first of all set BL to high voltage, then the read operation start through the special word line R. CBL connect to high and the CBLB is connected to low voltage and remains at high voltage. By simulation result we have observed that proposed 11T RAM cell generates Q and QB output which has proper logic with proper output waveform. The output waveform for proposed 11T RAM cell is shown in Fig. 4. Word A1 Word A2 Word Ak A 11 A 12 A 1n A 21 A 22 A 2n A k1 A k2 A kn (a) A 11 A 21 A k1 A 12 A 22 A k2 A 1n A 2n A kn 1st bit 2nd bit nth bit (b) Fig.5 RAM word organization (i) hared word line (ii) Bit-interleaving Bit-interleaving is commonly used in RAM design for soft error protection as well as area efficient utilization of wiring. Fig. 6 shows 2x2 bitinterleaving architecture of proposed 11T RAM design. The detail explanations 2x2 array of the bitinterleaving architecture is given in [12]. <0>= elected column Half-selected Column R<0>=0 <1>= Half-selected Cell Non-elected cell CBL<0 BL<0> CBLB<0> CBL< 1 BL<1> CBLB<1> R<1>= Fig.4. Output Waveform of design Fig.6 The 2x2 bit-interleaving architecture of 11T RAM cell 3.2 Concept of Bit-interleaving architecture RAM architecture has mainly two ways to arrange the words. hared word line shown in Fig. 5(i) and bit interleaving shown in Fig. 5(ii). In share word line, all the bits of the same words are located next to each other shown in Fig.5. This design is most common because of its simplicity and compactness but the bits are adjacent to each other that cause the probability of multi-bit soft errors is very high. To solve the problem of soft errors the 2 nd architecture i.e. bit interleaving architecture is used. A detailed explanation of bit-interleaving concept is explained in [8]. IV. CELL PERFORMANCE ANALYI In this section, cell properties such as NM, peed, Power consumption, PDP etc. are compared with the existing design, namely the standard 6T cell and 9T cell. All the existing and proposed circuit is simulated using the tool Cadence Virtuoso at 180nm technology. Power consumption and delay is calculated at different supply voltages 1.8V, 1.6V and 1.4V respectively. We observed that as the supply voltage scale down the power consumption of the RAM cell also reduces but it also affected cell stability. The size of the transistors is taken to be the same for all transistor of the cell for comparison of different type of RAM designs. IN: Page 69

4 4.1 peed and power analysis The proposed design shows 73.88% reduction in power, 71.53% reduction in PDP at 1.8V with respect to standard 6T RAM and 9.89% reduction in power, 29.11% reduction in PDP at 1.8V with respect to existing 9T RAM as shown in table-i. The significant improvement at other voltages can be analysed from the Table-II and Table-III. The proposed circuit has been mainly designed with bitinterleaving capability with better performances compared 9T RAM in term of power, speed, PDP and stability. Table I: - Power consumption and Delay of existing and proposed RAM cell at 1.8V RAM CELL Power(µW) Delay(p) PDP (fw) 6T RAM T RAM T RAM Table II: - Power consumption and Delay of existing and proposed RAM cell at 1.6V RAM CELL Power(µW) Delay(p) PDP (fw) 6T RAM T RAM T RAM Table III: - Power consumption and Delay of existing and proposed RAM cell at 1.4V RAM CELL Power(µW) Delay(p) PDP (fw) 6T RAM T RAM T RAM Fig.7. Variation of power and PDP with supply voltages 4.2 tability Analysis The stability of RAM cell is defined by static noise margin (NM); the higher the NM the better the stability. NM can be defined the maximum DC noise voltage that can be tolerate by the cell without changing the output bit or stored bit. o the cell stability is depends on supply voltage, as supply voltage is reduce the cell become less stable. The most common static approach for measuring the NM is by using butterfly curves, and this curve can be obtain by dc analysis. The NM of the RAM cell is defined as the size of the largest square that can fit into the butterfly curve [10] Hold stability The hold stability of the RAM is defined by the HNM (Hold NM). In 9T and proposed 11T cell the butterfly curve appear asymmetrical due to the asymmetrical stored structure. Hence the HNM equals to the smaller one of the two maximum squares. Butterfly curves for HNM calculation is shown in Fig. 8. NM = min (NM 1, NM 2) (a) (b) (c) Fig.8. tatistical butterfly curves of Hold mode (a) 6T (b) 9T (c) 11T IN: Page 70

5 4.2.2 Write stability Write stability of RAM cell can be analyzed by Write static Noise Margin (WNM). The definition of the conventional WNM based on the butterfly curve as shown in Fig.9. More WNM shows better stability. (a) (b) (c) Fig.9. tatistical butterfly curves of write mode (a) 6T (b) 9T (c) 11T Read stability Read stability of RAM cell also can be analyzed by Read static Noise Margin (RNM). The definition of the conventional RNM based on the butterfly curve as shown in Fig.10. More RNM shows better the read stability. V. CONCLUION In this paper, a novel 11T RAM cell with bitinterleaving capability has been proposed. The proposed design shows reduction in power consumption, improvement in the stability and PDP at the cost of area overhead. Analysis of results show that, the proposed 11T RAM cell is giving better performance in terms of stability, power consumption and PDP with respect to standard 6T RAM cell and 9T RAM with bit-interleaving capability. The delay of the circuit is increased slightly at the voltages above 1.6V in comparison with that of standard 6T RAM cell but PDP of the circuit reduces in significant amount at all the voltages. While significant reduction in both delay and power consumption is observed with respect to 9T RAM. And proposed design is more stable and robust compared with the existing designs. REFERENCE [1] W. R. E. Aly and M. A. Bayoumi, "Low-power cache design using 7T RAM cell ", IEEE Trans. Circ. ys., vol. 54, no. 4,pp , April [2]. A. Tawfik and V. Kursun, "Low power and roubst 7T dual- Vt RAM circuit", in Proc. IEEE Int. ymp. Circ. ys., ICA 2008, eatle, W A, UA, 2008, pp [3] B.H. Calhoun, J.F. Ryan,. Khanna, et al., Flexible circuits and architectures for ultralow power, Proc. IEEE, 2010, vol. 98, pp (a) (b) (c) Fig.10. tatistical butterfly curves of read mode (a) 6T (b) 9T (c) 11T The table IV shown below has the comparative analysis of the different RAM designs. The table clearly shows that the proposed design is giving better performances in term of stability as compare with existing 6T and 9T RAM design in all three modes i.e. hold mode, read mode and write mode. Table IV: - NM of existing and proposed RAM cell at 1.8V RAM CELL HNM WNM RNM 6T RAM 528 mv 460 mv 83 mv 9T RAM 516 mv 533 mv 71 mv 11T RAM 558 mv 583 mv 107 mv [4] Ik Joon Chang, Jae-Joon Kim, et al., A 32 kb 10T subthreshold RAM array with bit-interleaving and differential read scheme in 90 nm CMO, IEEE J. olid-tate Circuits vol. 44, no. 2, pp , Feb [5] Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsan, et al., A single-ended disturbfree 9T subthreshold RAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing, IEEE J. olid-tate Circuits vol. 47, no. 6, pp. 1 14, June [6] Meng-Fan Chang, hi-wei Chang, Po-Wei Chou, et al., A 130 mv RAM with expanded write and read margins for subthreshold applications, IEEE J. olid-tate Circuits vol. 46, no.2, pp , Feb [7] Ming-Hung Chang, Yi-Te Chiu, Wei Hwang, et al., Design and Iso-area vmin analysis of 9T subthreshold RAM with bitinterleaving scheme in 65-nm CMO, IEEE Trans. Circuits yst. II: vol. 59, no.7, pp , July [8] Anh-Tuan Do, Jeremy Yung hern Low, Joshua Yung Lih Low, et al., An 8T differential RAM with improved noise margin for bit-interleaving in 65 nm CMO, IEEE Trans. Circuits yst. I Regul.vol. 58, no. 6, pp , June [9]. Hanson, B. Zhai, K. Bernstein, et al., Ultralow-voltage, minimum-energy CMO, IBM J. Res. Develop,vol.50, pp , [10] E. eevinck et al., tatic-noise margin analysis of MO RAM cells, IEEE J. olid-tate Circuits, vol. C-22, no. 2, pp , May IN: Page 71

6 [11] Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, et al., A read-static noise-margin-free RAM cell for low-vdd and high-speed applications, IEEE J.olid-tate Circuits, vol. 41, no.1, pp , Jan [12] Liang Wen, Zhikui Duan, Yi Li, Xiaoyang Zeng, Analysis of a read disturb-free 9T RAM cell with bitinterleaving capability, Microelectronics Journal, vol. 45, pp , mar [13] K. khare, R. Kar, D. Mandal,.P. Ghosal, Analysis of leakage current and leakage power reduction during write operation in CMO RAM cell IEEE international conference on communication and signal processing, April 2014, pp [14] J. ingh, 1. Mathew, and K. D. Pradhan, "A subthreshold single ended I/O RAM cell design for nanometer CMO technologies", in Proc. IEEE Int. OC Conf. OCC, 2008, pp [15] P. Hazucha, T. Karnik, and J. Maiz, et al., Neutron soft error rate measurement in 90-nm CMO process and scaling trends in RAM from 0.25-um to 90-nm generation, in: Proc IEDM Technical Digest, 2003, pp IN: Page 72