Advanced Digital Integrated Circuits. Lecture 9: SRAM. Announcements. Homework 1 due on Wednesday Quiz #1 next Monday, March 7

Transcription

1 EE241 - Spring 2011 Advanced Digital Integrated Circuits Lecture 9: SRAM Announcements Homework 1 due on Wednesday Quiz #1 next Monday, March 7 2 1

2 Outline Last lecture Variability This lecture SRAM 3 Practical Variability-Aware Design Will be covered in next several lectures SRAM design Statistical timing analysis 4 2

3 SRAM Read/Write/Retention Margins SRAM Scaling Trends 100 m 2 ) ITRS Single Cell Reported Individual Cell Reported Cell in Array m 2 ) ITRS Effective Cell Reported Effective Cell SRAM Cell Size (u 10 1 SRAM Cell Size (u x effective cell area scaling difficult Technology Node (nm) Technology Node (nm) Individual SRAM cell area able to track ITRS guideline Array area deviates from ITRS guideline at 90nm Memory design no longer sits on the 0.5x area scaling trend! 6 3

4 Memory Scaling ze (MB) On-Die L3 Cache siz 10 1 Server processors Itanium Processors Technology Node (nm) Xeon Processors Memory latency demands larger last level cache (LLC) Memory is more energy-efficient than logic LLC approaches 50% chip area for desktop and mobile processors LLC approaches 80% chip area for server processors Vivek De, Intel T SRAM Cell Improve CD control by unidirectional poly Relax critical layer patterning requirements Optimizing design rules is key 8 4

5 SRAM cell design trends B IEDM 02 V DD GND WL Cell in 90nm (1 m 2 ) Cell in 32nm (0.171 m 2 ) Shorter bitline enables better cycle time and/or array efficiency Full metal wordline with wider pitch achieves better RC 9 SRAM Cell Trends A little analysis with a ruler: Aspect ratio 2.9 Height ~178nm, Width ~518nm Gate ~ 45nm (Lg is smaller) m 2 cell in 22nm from Intel (IDF 09) m 2 cell in 45nm from Intel (IEDM 07) 10 5

6 More SRAM Trends 0.15 m 2 cell in 32nm from TSMC (IEDM 07) 0.1 m 2 cell in 22nm from IBM (IEDM 08) 11 Ion/Ioff: Cell Read and Leakage H. Pilo, IEDM

7 13 SRAM Cell/Array Hold (retention) stability WL Read stability M 2 VDD M 4 Write stability M5 Q Q M6 Read current (access time) M1 M3 Access Transistor Pull down Pull up 14 7

8 SRAM Design Hold (Retention) Stability WL Load PL V DD PR AXL 1 AXR 0 NL NR Access NPD Scaling trend: Data Retention Leakage Increased gate leakage + degraded I ON /I OFF ratio Lower V DD during standby PMOS load devices must compensate for leakage 15 Retention Stability Would like to reduce supply in standby WL PL V DD PR AXL 1 0 AXR NL NR 16 8

9 Monte-Carlo Simulation of DRV Distribution 300 stogram of cell # Hi Qin, ISQED Simulated DRV of 1500 SRAM cells (mv) 17 H. Pilo, IEDM

10 Read Stability Static Noise Margin (SNM) VDD 1 VL VR PR AXR Read SNM NR VR (V) nm simulation VL (V) Read SNM is the contention between the two sides of the cell under read stress. 1 VTh Due to RDF C WL E. Seevinck, JSSC 1987 ox 19 Read SNM - Measurements WL Load V DD PL PR AXL 1 Access NL NR AXR V>0 NPD Retention fluctuations Read margin and retention margin [Bhavnagarwala, IEDM 05] 20 10

11 Read Stability N-Curve A, B, and C correspond to the two stable points A and C and the metastable point B of the SNM curve When points A and B coincide, the cell is at the edge of stability and a destructive read can occur 21 H. Pilo, IEDM

12 Write Stability Write Noise Margin (WNM) VDD PR VL VR AXR NR Writeability is becoming harder with scaling Optimizing read stability and writeability at the same time is difficult A. Bhavnagarwala, IEDM Write Stability /WL Write Margins (V) Voltage WM 0.00E E E E E E-07 Time (s) Highest voltage under which write is possible when C is kept precharged (V) Voltage ( WM WL 0.00E E E E E E-07 Time (s) Difference between VDD and lowest WL voltage under which h write is possible when both bit-lines are precharged 24 12

13 Write Stability Write Current (N-Curve) Minimum current looging into the storage node C. Wann et al, IEEE VLSI-TSA H. Pilo, IEDM

14 6-T SRAM Static/Dynamic Stability Read Margin SNM: pessimistic Write Margin WNM: optimistic Introduction of dynamic margins 27 Next Lecture SRAM design techniques 28 14

15 SRAM Assist Techniques Peripheral Circuits to Help SRAM Write assist techniques Read assist techniques Redundancy ECC 30 15

16 Multi-Voltage SRAM Read Write Retention WL Periphery Vmin Vmin Vmin AXL V DD PL PR 1 0 NL NR AXR Precharge Vmin (H) Vmin (L) Vmin WL Vmin Vmax N/A Cell V DD Vmax Vmin Vmin 31 Array Adjustments Array back bias, to compensate for systematic variations S. Mukhopadhyay, VLSI

17 Dynamic V DD Implementation WL cell cell cell cell cell WL cell cell cell cell cell BI MUX VCC MUX VCC_hi VCC_lo W R R R MUX (8:1) MUX MUX MUX MUX MUX VCC selection is along column direction to decouple the read & write Zhang, ISSCC Capacitive Write Assist S. Ohbayashi, VLSI

18 Write/Read Assist H.Pilo, VLSI Pulsed WL/ M.Khellah, VLSI

19 Negative 0V Negative bias gen Din Nii, VLSI SRAM Redundancy and ECC 19

20 Redundancy and ECC in SRAM Redundancy Redundant columns If a faulty cell is detected during test, the entire column is replaced Error correction codes Protect form random soft errors 39 ECC Kawahara, ISSCC 07 tutorial 40 20

21 Multi-bit Errors Kawahara, ISSCC 07 tutorial 41 Multi-bit Errors Kawahara, ISSCC 07 tutorial 42 21

22 Multi-bit Errors 43 Multi-bit Errors: Interleaving 44 22