Design and verification of low power SRAM system: Backend approach

Transcription

1 Design and verification of low power SRAM system: Backend approach Yasmeen Saundatti, PROF.H.P.Rajani E&C Department, VTU University KLE College of Engineering and Technology, Udhayambag Belgaum , Karnataka, INDIA ABSTRACT- Leakage power loss is a major concern in deep-submicron technologies. Highperformance processors and servers consume enormous amount of operating power. For portable devices that have burst-mode type integrated circuits, it is acceptable to have leakage during active mode. However, during the idle state it is extremely wasteful to have leakage, as power is unnecessarily consumed with no useful work being done. Efficient leakage control mechanisms are crucial for saving power. In this work the performance of 6T standard SRAM is compared with low power asymmetric SRAM and SRAM with AVLG and AVLS control circuits. The static power, total power is measured at different temperatures. The access time is also calculated for write as well as read operations. An entire memory system for 8 bit X 8 bit along with all peripherals is designed and simulated. Layout is also drawn which has passed DRC, LVS and RCX. Key words: SRAM, leakage power, AVLG SRAM, AVLS SRAM, static power,. INTRODUCTION Fast low power SRAMs have become a critical component of many VLSI chips. This is especially true for microprocessor, where the on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and the main memory [5-6]. Simultaneously, power has become an important consideration both due to the increased integration and operating speeds, as well as due to the explosive growth of battery operated appliances. In this work the performance of the SRAM memory system is improved by reducing leakage current and power. We compare the results of conventional 6T SRAM cell, with an asymmetric SRAM cell. An adaptive voltage level (AVL) circuit is added to 6t SRAM cell, to reduce the sub-threshold leakage.avl circuit controls the effective voltage across the SRAM cell in inactive mode. An AVL circuit can be used either at the upper end of the SRAM cell to reduce the supply voltage (AVLS) or at the lower end of the SRAM cell to raise the potential of the ground node of the cell (AVLG) As compared to previous paper mentioned in [2] here we are incorporating the full SRAM read/write circuitry, pre charge circuit and sense amplifier circuit along with the layout of all the circuit designs and measurement of the static and total power of all the circuits. Simulations are performed with cadence 180nm CMOS technology process file using spectre tool. Power of all the cells are measured and compared. 1. Basic 6T SRAM cell: It consists of pair of cross coupled inverters that use positive feedback to store value. Transistors M5 and M6 are 2 pass transistors that allow access to the storage nodes for reading and writing. To write a value into a SRAM cell the new value and its complement is driven on the bit lines and then the word line is raised. The new will overwrite the old value, since the bit lines are actively driven by write circuitry. To read a value from an SRAM the bit lines are pre charged high and the word line is raised turning on the pass transistors. Because one of the internal storage node is low, one of the bit line starts discharging. A sense amplifier which is connected to the bit line senses which of the bit line is discharging and reads the stored value. The 6T SRAM cell is designed such that the pull up p-transistors are weakest, access transistors are of medium strength and pull-down nmos transistors are strongest to satisfy write and read constraints as mentioned in[3] simulated and verified using cadence spectre tool in 180nm technology. The 6T SRAM cell is as shown in figure1. The simulation signals for writing 1 and 0 are as shown in figure 2. The layout is also drawn for physical verification and found to give no DRC errors and correct functionality was observed for post layout simulation. IJCSIET-ISSUE2-VOLUME2-SERIES2 Page 1

2 Now we consider two cases: Case 1 when 0 is stored in the cell: Figure1. 6T SRAM Cell Node q=0, bit line bar(blb)=1, and M6 passes week 1, the drain voltage of the transistor M2 is less than the supply voltage(m2=vdd-vth, where Vth is the threshold voltage of the transistor M6). Due to this gate-source and gate-drain voltage of the transistor M1 also reduces, even the gate leakage current of the transistor M2 and M6 also reduces due to the reduction in their gate-source and gate-drain voltage. The sub threshold leakage through transistor M2 also reduces due to reduction in its Vds. Case 2 when 1 is stored in the cell: Figure 2. SRAM Simulated Waveform. Node q=1 voltage at node QBAR and DQBAR is 1 and there is no reduction in leakage current of cell, but an extra gate leakage current appears through M7, since its gate voltage is 1. However as most of the bits stored in SRAM are 0 s, the number of 0 s are greater than number of 1 s; hence there is significant reduction in leakage current. The node DQBAR in the circuit acts as a dummy storage node and static noise margin of the cell does not get affected. 2.1 Read operation in asymmetric SRAM cell: when 0 is stored in the cell, The conductance of the transistor M1 reduces since drain voltage of the transistor M1 also reduces from VDD to VDD-Vth [7]. During read operation when 0 is stored in the cell the bit line(bl) is discharged, and the discharge time which is small fraction of the total read access time increases by little amount which is tolerable. Figure 3. 6t SRAM cell layout 2. Asymmetric SRAM cell: The modified version of 6T SRAM cell is Asymmetric SRAM cell. The asymmetric SRAM cell is developed to reduce the gate leakage current and sub threshold leakage as mentioned in [7]. The circuit diagram and layout are as shown in fig 4 and 5.The gate leakage current in a transistor reduces as its gate/drain or gate/source voltage is reduced. The sub threshold leakage can be reduced by reducing its drain-source voltage. Asymmetric SRAM cell makes use of an extra nmos transistor M7 that reduces the gate/source or gate/drain voltage of the transistor that dissipates gate leakage when a 0 is stored in the cell. 2.2 Write Operation in asymmetric SRAM cell: Node QBAR controls the operation of writing 1 into the asymmetric SRAM cell, rather than DQBAR, because voltage at node DQBAR will start reducing only when the voltage at node QBAR, reaches the value equal to that of DQBAR, and then both will be discharged identically. This is because, when the voltage at node QBAR is VDD, the nmos transistor M7 will pass it as VDD-Vth as its gate voltage is VDD.while discharging, the voltage at node QBAR will remain at VDD-Vth as long as the voltage at node QBAR is in the range (VDD-Vth, VDD) and after that both values will be the same and move towards 0 identically. IJCSIET-ISSUE2-VOLUME2-SERIES2 Page 2

3 Further, a new sub threshold leakage current appears in M6 due to the reduction in drain voltage. This additional sub threshold leakage current through access transistor can be reduced by making the bit lines floating. Hence, this approach is more successful in reducing gate leakage currents than AVLG but still leaves two gate leakage current components unaltered. Figure4. Asymmetric SRAM Figure6. AVLS SRAM cell Figure5. Asymmetric SRAM layout 3. An Adaptive Voltage Level (AVL) Control Circuit: An AVL circuit can be used either at the upper end of the SRAM cell to reduce the supply voltage(avls) or at the lower end of the SRAM cell to raise the potential of the ground node of the cell(avlg). These two techniques are described as below in the later sections. 3.1 An Adaptive Voltage Level Control Circuit near Supply Voltage (AVLS): An AVLS circuit consists of full 6 transistor SRAM cell with an additional voltage level control circuit near supply voltage as shown in figure 6. The layout of AVLS is as shown in figure 7. Here a full supply voltage of VDD is applied to SRAM in active mode while a reduced supply voltage of VD is applied in inactive mode. Since transistor M4 is in ON state, the drain voltages of transistors M2 and M1 are also at VD [3]. The gate leakage current of transistors M1 and M2 get reduced due to the decrease in their gatesource and gate-drain voltages respectively. A decrease in source voltage of transistor M6 results in a decrease in gate leakage through it. The gate leakage through transistor M5 remains unchanged. The sub threshold leakage currents are reduced in transistors M2 and M3 but remain unaltered in M3. Figure7. AVLS SRAM layout 3.2 An Adaptive Voltage Level Control Circuit Near Ground (AVLG): An AVLG circuit consists of full 6t SRAM cell with an additional adaptive voltage level control circuit near ground as shown in figure 8. The layout of AVLG is as shown in figure 9. An AVLG circuit provides 0 volt at the ground node during the active mode to SRAM cell and a raised ground level (virtual ground) during the inactive mode. An increase in virtual ground voltage reduces the gate-source and gate-drain voltage of transistor M1 and also the gatedrain voltage of transistor M2, which results in a sharp reduction in gate leakage currents of these two transistors. There is no improvement in gate leakage IJCSIET-ISSUE2-VOLUME2-SERIES2 Page 3

4 currents of transistors M5 and M6. But an additional gate leakage appears in transistor M5 due to decrease in drain voltage of M1. Incorporation of AVL results in another new gate leakage current through nmos transistor NL1 in the AVL switch. AVLG approach successfully reduces sub threshold leakage currents through M3, M2 and M5 as well [3]. Thus AVLG approach is completely successful in reducing all sub threshold leakage currents but it is only partially successful in reducing gate leakage currents. two output signals are OUT corresponding to the data signal and OUTBAR is the inverse of OUT [3]. The layout of one bit SRAM read/write column circuit is shown in fig 11, which has passed the DRC, LVS and RCX. Figure 12 shows the simulated waveform of one bit SRAM read/write column circuit. Similarly one bit AVLS SRAM read/write column circuit is designed simulated and verified. Figure 13 shows the schematic of one bit AVLS SRAM read/write column circuit and the layout of one bit AVLS SRAM read/write column circuit are shown in fig 14, which has passed the DRC, LVS and RCX. Figure8. AVLG SRAM cell Figure10. One bit SRAM read/write column circuit... Figure9. AVLG SRAM layout 4. 1 BIT SRAM AND AVLS SRAM READ/WRITE COUMN: Combining the circuits namely, write driver,pre charge, SRAM cell, column mux and sense amplifiers, one write and read cell is obtained. The complete schematic of one write and read cell is shown in figure 10. The input signals are write _enable (WE) that allows writing of data to the cell, sense amplifier enable (SAE) that allows reading of data from the cell, word enable that decides to/from which address data will be written or read from and the signal data (VIN) is the one bit data either high or low that is to be stored to or read from the cell. The Figure11. Layout of one bit SRAM read/write column circuit.. IJCSIET-ISSUE2-VOLUME2-SERIES2 Page 4

5 Figure13. one bit SRAM read/write column circuit. Figure12 One bit SRAM read/ write timing diagram. Figure14. Layout of one bit SRAM read/write column circuit BIT 8X8 SRAM SYSTEM: 8-bit X 8-bit SRAM system is R/W memory circuit that permits the writing of data bits to be stored in a memory array, as well as reading of data bits stored in a memory array. The SRAM system is developed using the cadence IC design environment. The SRAM system design consists of SRAM cells, pre charge, sense amplifier, column multiplexer, and row IJCSIET-ISSUE2-VOLUME2-SERIES2 Page 5

6 decoder. The most important part is the cell as all the other circuitry is connected to and around the cell. The popular, full CMOS 6T cell configuration is used to design the SRAM memory array [1]. The full SRAM system is as shown in figure 15. Some of the advantages of using full CMOS SRAM configuration are low static power, high switching speeds and suitability for high density SRAM arrays. In order to design a 64 bit SRAM, 64 full CMOS 6T SRAM cells are used. Each SRAM cell has a capability of storing 1 bit. Table2: power of Asymmetric SRAM cell Temp ( C) Ptotal Pstatic nW pW nW 8.441pW nW 17.97pW nW 62.17pW nW pW nW pW nW pW Table3: power of AVLS SRAM cell Temp ( C) Ptotal Pstatic nW pW nW pW nW pW nW 62.09pW nW pW nW pW nW pW Figure15. 8x8 SRAM system read/write circuit 6. Simulation Results: Simulations are performed using cadence design environment in 180nm CMOS technology using spectre tool with a supply voltage of VDD=1.8V. The static power, dynamic power and the total power are measured for all the different types of SRAM cells at different temperatures are as shown in below table 1, 2, 3, and 4. The access time calculations of all the cells are measured at a temperature of 27 c are as shown in below table 5. The layouts of different types of SRAM cells are designed and measured using cadence assura tool in 180nm technology are as shown in below table 5. Table1: power of SRAM cell Table4: power of AVLG SRAM cell Temp ( C) Ptotal Pstatic nW 6.704pW nW 8.441pW nW 17.97pW nW 62.18pW nW pW nW pW nW pW Table 5: Area and Access time calculation of different types of SRAM cells. Temp Ptotal Pstatic ( C) nW pW nW pW nW pW nW 62.18pW nW pW nW pW nW pW NAME AREA(λ) ACCESS TIME SRAM 8.755X ps Asymmetric X ps SRAM AVLG SRAM X ps AVLS SRAM X ps IJCSIET-ISSUE2-VOLUME2-SERIES2 Page 6

7 7. Conclusion: An AVLS SRAM cell proposed offers reduced gate and sub threshold leakage currents and power in caches. Simulation results show that there is a significant reduction in the total leakage power that was achieved at 27 c with marginal degradation in the performance compared to the conventional 6T SRAM cell. Two schemes: a) raising the ground level and b) decreasing the supply voltage to the SRAM cell during inactive mode to suppress its leakage power were also examined in detail. It was observed that the scheme using supply voltage reduction is more efficient than the one raising the ground potential. The access time is reduced significantly in AVLG SRAM compared to other SRAM cells. The SRAM system is developed using cadence IC design environment. The design is based on the 180nm technology process. 8. References: 1. CMOS VLSI Design- a Circuits and systems perspective. Third edition-neil H.E.WESTE, Macquarie university and the university of Adelaide, David HARRIS, Harvey Mudd College, Ayan Banerjee, Bengal Engineering and Science University. 2. Leakage power estimation in SRAM S by Mahesh Mamidipaka, Kamal Khouri, Nikhil Dutt, Magdy Abadir. CECS Technical Report#03-32.Centre for Embedded Computer Systems, University of California, Irvine, CA 92697, USA 3. M.D.Powell, S.H.Yang, B.Falsafi etal Gated- VDD: A circuit technique to reduce leakage in cache memories. In proceedings of International Symposium on Low Power Electronics and Design, July Tutorial cadence design environment by Antonio J.Lopez Martin. 5. S.Borkar.Design challenges of technology scaling.ieee Micro, 19(4):23-29, august T.Enomoto.Y.Oka and H.Shikano. self controllable voltage level( SVL) circuits, 38(7): ,july Navid Azizi, Farid N.Najm.Andreas Moshovos.Low leakage asymmetric cell SRAM.IEEE transactions on VLSI systems, 11(4): ,August2003. IJCSIET-ISSUE2-VOLUME2-SERIES2 Page 7