EE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements

Transcription

1 EE241 - Spring 2007 Advanced Digital Integrated Circuits Lecture 22: SRAM Announcements Homework #4 due today Final exam on May 8 in class Project presentations on May 3, 1-5pm 2 1

2 Class Material Last lecture Technology and environment variability Today s lecture SRAM 3 SRAM Scaling Trends 100 SRAM Cell Size (um 2 ) 10 1 ITRS Single Cell Reported Individual Cell Reported Cell in Array SRAM Cell Size (um 2 ) x effective area scaling difficult ITRS Effective Cell Reported Effective Cell Technology Node (nm) Technology Node (nm) Individual SRAM area able to track ITRS guideline Array area deviates from ITRS guideline at 90nm Memory design no longer sits on the 0.5x area scaling trend! 4 2

3 Memory Scaling On-Die L3 Cache size (MB) 10 1 Server processors Itanium Processors Technology Node (nm) Xeon Processors Memory latency demands larger last level cache (LLC) Memory is more energy-efficient than logic LLC approaches 50% chip area for desktop and mobile processors LLC approaches 80% chip area for server processors Vivek De, Intel T SRAM Cell Improve CD control by unidirectional poly Relax critical layer patterning requirements Optimizing design rules is key Vivek De, Intel

4 SRAM design trends B IEDM x1.24μm GND Cell in 90nm (1μm 2 ) Improve CD control by unidirectional poly Relax critical layer patterning requirements Optimizing design rules is key Cell in 65nm (0.57μm2) Shorter bitline enables better cycle time and/or array efficiency cy Full metal wordline with wider pitch achieves better RC 7 Ion/Ioff: Cell Read and Leakage 8 H. Pilo, IEDM

5 SRAM Cell/Array Read stability Write stability M 2 VDD M 4 Read current M5 Q Q M6 M1 M3 Access Transistor Pull down Pull up 9 SRAM Design Hold (Retention) Stability Load PL PR AXL 1 AXR 0 NL NR Access NPD Data Retention Leakage Scaling trend: Increased gate leakage + degraded I ON /I OFF ratio Lower during standby PMOS load devices must compensate for leakage 10 5

6 V 2 (V) The Data-Retention Voltage (DRV) of SRAM 0 M 5 V 1 Leakage current M 1 M 2 M 3 M 4 V 2 0 M 6 Leakage current DRV Condition: V V 1 1 = = 2 Left inverter V V 2 Right inverter, when VDD DRV 0.4 VTC of SRAM inverters When V dd scales down to DRV, the Voltage Transfer Curves (VTC) of the internal inverters degrade to such a level that Static Noise Margin (SNM) of the SRAM reduces to zero =0.18V =0.4V VTC 1 VTC 2 Qin, ISQED V 1 (V) 11 Monte-Carlo Simulation of DRV Distribution 300 Histogram of # Simulated DRV of 1500 SRAM s (mv) 12 6

7 H. Pilo, IEDM Read Stability Static Noise Margin (SNM) 1 Read SNM[1] VR (V) 0.5 Read SNM is typically the most stringent constraint SNM shrinks with each generation [1] E. Seevinck, JSSC nm simulation VL (V) 14 7

8 SRAM Design Read Stability Load PL PR 1 AXL Access NL AXR V>0 NR NPD Retention fluctuations Read margin and retention margin [Bhavnagarwala, IEDM 05] 15 Read Stability N-Curve A, B, and C correspond to the two stable points A and C and the metastable point B of the SNM curve When points A and B coincide, the is at the edge of stability and a destructive read can easily occur [1] E. Seevinck, JSSC

9 H. Pilo, IEDM Write Stability Write Noise Margin (WNM) 1 90nm simulation VR (V) 0.5 WNM[1] VL (V) Write stability is becoming more stringent with scaling Optimizing read and write stability at the same time is difficult [1] A. Bhavnagarwala, IEDM

10 Write Stability Traditional Write Margin (TWM) Voltage (V) WM E E E E E E-07 Time (s) Voltage (V) WM E E E E E E-07 Time (s) Highest voltage under which write is possible when C is kept precharged (left) Difference between VDD and lowest voltage under which write is possible when both bit-lines are kept precharged (right) Can be directly measured in large memory arrays via currents 19 Write Stability Write Current (N-Curve) [1] C. Wann et al, IEEE VLSI-TSA

11 H. Pilo, IEDM SRAM Design Read/Write Stability Load Cell Stability PL AXL 1 Access NL PR AXR V>0 NR Voltage Cell Trip Voltage Cell Read Voltage Read Upset Occurs NPD Read margin is typically the most stringent constraint Cell read voltage must stay below trip voltage Harder to achieve with process induced variations Noise margin degraded with technology scaling Technology Scaling H. Pilo, ISSCC

12 H. Pilo, IEDM H. Pilo, IEDM

13 H. Pilo, IEDM Multi-Voltage SRAM Read Write Retention Periphery Precharge Vmax N/A Cell Vmax Cell well Vmax Vmax Vmax 26 13

14 Dynamic Implementation BI MUX VCC MUX VCC_hi VCC_lo W R R R MUX (8:1) MUX MUX MUX MUX MUX VCC selection is along column direction to decouple the Read & Write Zhang, ISSCC The Rest in Class Presentations Read/Write assist circuits Alternate s for subthreshold operation FinFET/double-gate designs Column design techniques Leakage suppression Sense amps 28 14

15 SRAM Scaling Approaching fundamental limits: Don t scale size Increase transistor count (from 6) Change technology (e.g. double-gate FETs) edram Or something else 29 Other SRAM Alternatives 8-T SRAM [1] Dual-port read/write capability (register file like s) N0, N1 separates read and write No Read SNM constraint Half-selected s still undergo read stress no single write capability Stacked transistors reduce leakage [1] L. Chang, VLSI Circuits

16 edram Process cost: Added trench capacitor Barth, ISSCC 07, Wang, IEDM Next Lecture Latches and flip-flops 32 16