SRAM MEMORY ARCHITECTURE. Student Name: Purnima Singh Roll Number :

Transcription

1 SRAM MEMORY ARCHITECTURE Student Name: Purnima Singh Roll Number : BTP report submitted in partial fulfilment of the requirement for the Degree of B.Tech in Electronics and Communication Engineering On BTP ADVISOR Vish Viweswaran Indraprastha Institute of Information Technology New Delhi

2 Student's Declaration I hereby declare that the work presented in the report entitled SRAM ARCHITECTURE" submitted by me for the partial fulfilment of the requirements for the degree of Bachelor of Technology in Electronics & Communication Engineering at Indraprastha Institute of Information Technology, Delhi, is an authentic record of my work carried out under guidance of Vish Visweswaran.Due acknowledgements have been given in the report to all material used. This work has not been submitted anywhere else for the reward of any other degree. Purnima Singh Certificate This is to certify that the above statement made by the candidate is correct to the best of my knowledge.... Place & Date:.....(advisors' name)...

3 Abstract Static Random Access Memory (SRAM) along with CMOS technology is scaling in different processors and system-on-chip (SoC) products rapidly and this has given us the need of innovation in the area of SRAM design. As, designing a larger SRAM cell would help us to reduce variations and increase the stability. Multiple assist schemes and design strategies has been used to increase the stability of memory cell as the role of these Assist schemes is to help in achieving a robust read or write operation This report presents the complete design of the SRAM sub-system architecture. The functioning of all the blocks of the architecture is explained in detail. Then the simulation of the complete architecture is given with the sizing of transistors and setting the initial conditions on cadence.

4 Acknowledgments Towards the end of my B.Tech. degree, I would like to pay my gratitude to several individuals who contributed from various perspectives. First of all, I would like to express my profound gratitude to my BTP mentor and Advisor, Vish Visweswaran for his support, and motivation all along the way. He has been a great source of inspiration for me. I would like to thank my professor at IIITD Dr.Mohammad Hashmi for providing a positive learning atmosphere to work and for the help he gave me through which understanding and working on this environment became less difficult for me.

5 Contents 1 Introduction 1. Memory classifications 2. Types of Memory 3. Architecture and Building Block 2 SRAM 1. SRAM Cell 2. 6T SRAM Cell operations Read Mode Write Mode 3 6T SRAM Cell at low Voltage 1. Reduced Noise Margin during Read Operation 2. Stability Issue during Write at Low Voltage 3. Assist Circuits 4 Simulations Results and Sizing of transistors 5 Summary and problem addressed 6 References 1

6 1. INTRODUCTION Semiconductor memory technology is an essential element of today's electronics. It is an electronic data storage device, often used as computer memory. With the rapid growth in the requirement for semiconductor memories there have been a number of technologies and types of memory that have emerged such as ROM, RAM, EPROM, EEPROM, Flash memory, DRAM and SRAM. Memory Classification Size: As memory is used to store data, we classify them on the basis of size. For example in case of a circuit design we express memory in terms of bits, whereas in case of hierarchy we talk about bytes,which is 8 bits and on a system level it is expressed in terms of words, which is collections of bytes. Function: Memories can also be classified on the basis of how they are accessed ( random or serial ). A random access memory can be accessed for read/write in a random fashion. On the other hand, in serial access memories, the data can be accessed only in a serial fashion. Types of semiconductor memory 1. Random Access Memory (RAM) is the best known form of computer memory. It is a type of a volatile memory, which means that the information can be accessed only till the power is on, it looses data as the power is off.

7 2. Read only memory (ROM) is an example of non-volatile memory. It holds the permanent data and can read it The types of ROM and RAM that are available are: a) DRAM: Dynamic RAM is a form of random access memory. It uses a capacitor to store each bit of data, and the level of charge on each capacitor determines whether that bit is a logical 1 or 0. However these capacitors do not hold their charge indefinitely, and therefore the data needs to be refreshed periodically. As a result of this dynamic refreshing it is named as dynamic RAM. b) SRAM: Static Random Access Memory. Unlike DRAM, the data does not need to be refreshed periodically in SRAM. It is able to support faster read and write times than DRAM. It consumes more power, is less dense and more expensive than DRAM. c) PROM: This stands for Programmable Read Only Memory. It is a semiconductor memory which can only have data written to it once - the data written to it is permanent. d) EPROM: This is an Erasable Programmable Read Only Memory. This form of semiconductor memory can be programmed and then erased at a later time. e) EEPROM: This is an Electrically Erasable Programmable Read Only Memory. Data can be written to it and it can be erased using an electrical voltage. f) Flash memory: Flash memory may be considered as a development of EEPROM technology. Data can be written to it and it can be erased, although only in blocks, but data can be read on an individual cell basis.

8 Memory Architecture and Building Blocks In a simplest way we stack the words linearly and to access a particular word we make the particular select line high. As shown in the figure below, N-word memory with N-select lines. But the problem arises in case of more number of data. To handle the issue, we use a decoder which decodes the address and the particular select line high.

9 But this does not solve our issue of memory aspect ratio (or height >> width). Such a design slower downs the process as the vertical wires connected to the cell are too long. So to bring the aspect ratio to unity a horizontal dimension is also bought such that both vertical and horizontal lines are equal in magnitude. Thus a column decoder is used. Now, To access a particular data both row decoder and column decoder are used and with the combination of both, the desired storage cell can accessed.

10 II. SRAM ARCHITECTURE 6T SRAM CELL The SRAM data storage cell, i.e., the one-bit memory cell consists of a two inverters connected back to back in a simple latch circuit with two stable operating points. Depending on the state of the two inverter latch circuit, the data being held in the memory cell will be interpreted either as logic '0' or as logic '1'. CMOS SRAM Cell The memory cell consists of simple CMOS inverters connected back to back, and two access transistors. The access transistors are turned on whenever a word line is activated for read or write operation, connecting the cell to the complementary bit line columns. The most important advantage of this circuit topology is that the static power dissipation [1] is very small; essentially, it is limited by small leakage current [2]

11 The SRAM cell here consist of a six- transistor, thus referred as 6T-SRAM cell. The two NMOS pass gate transistors (PG) are used to access the cell, therefore they are also termed as access transistors. Word line (WL) is used to access the pass gates transistors connected with the bit lines (BL and BLB) for read or write operations. BL and BLB are input /output lines which helps in reading/writing of the data 6T SRAM CELL OPERATION 1. Read Mode (the data has been requested): To read the data we first precharge both the bit-lines (Bit Line and Bit Line Bar) to the supply level, Vdd. Now we will make the word line (WL) high. As BL and BLB are connected to node 0 and 1 respectively through PG, the BL attached to node 0 starts discharging through PG and PD but the BLB attached to node 1 will still be closer to Vdd. Thus a small differential variation is occurred which is then evaluated by sense amplifier [3], which then give the read data.

12 2. Write Mode (updating the contents) :As sense amplifier is used to read data from the cell similarly while writing, write driver is used to write the data. First, we discharge bit lines (BT and BTB) with the help of write drivers [4]. As word line (WL) still high,the discharged bit line pulls down the node 1 through PG, but pull up transistor (PU) will try to repel this and would like to keep node 1 To have a successful write we want the data to flip (complementary value) therefore the combination of write driver and PG should be much stronger than PU,so that the data gets flipped.

13 III. 6T-SRAM Cell at Low Voltage The size of SRAM cell are always considered and are tried to kept small which require power saving while working at low voltages. But the stability and performance of the cell is also affected at low voltages. The low voltage reduces the Static Noise Margin [5] upon which the stability of the SRAM cell depends. Reduced Noise Margin during Read Operation We know while reading, we pre-charge both the bit lines, keeping WL low. Then we make WL go high due to which BL starts to get discharge through PGL and PDL. Due to this discharge, the node N0 will start rising (say delta V). The problem arises when the rise is more than the threshold of I2 [6] (fig above) which makes the data flip which we don't want. During a read operation, the data at N0 can be overwritten and the read failure occurs. Thus the difference between the delta V and the threshold of the inverter is Static Noise Margin. It is also measured through a butterfly curve.[7]

14 Stability Issue during Write at Low Voltage: Stability of a SRAM cell during write operation is defined by a parameter called Write Margin (WM). In order to write data we want N0 and N1 need to get complementary value of 1 and 0 respectively. To do this WL is made high and BL is discharged.due to this, N1 starts discharging through PGL while PUL opposes this discharge. Our write operation is successful only when PGL is stronger than PUL which will make the node N1 value 1 low. But if PGL is not strong enough to make the node pulled down, write failure occurs. Thus the required BL voltage at which successful write successful occurs is called write Margin. ASSIST CIRCUITS As we know SNM and WM affects the stability of the cell so to improve stability we require assist circuits [8].Read assist (RA) circuits intend to increase the static noise margin (SNM) of the memory cell, while write assist (WA) circuits helps to achieve a successful write operation. Sub-VDD Bit-line Pre-charge: In this scheme, bit lines are not precharged to full supply level. In order to have better SNM, we keep bit lines at much lower level, near to VDD/2 which result in reduction of cell current.

15 Word-Line Under-Drive: Word-line under-drive is most commonly used technique, it increase read stability of the memory cell. In this we keep wordline at a voltage lower than the supply voltage (sayvdd-deltav) Due to which, pass gate device weakens and increases the SNM. Negative Bit-Line Approach: This is the most widely used writeassist method.in this, bit-line is pulled down below 0 or below ground. The write drivers are off and negative charge is given to the bitlines, which strengthens the pass gate of cell. We know that as stronger is pass gate, the discharge of node 1 becomes faster. Memory-Column VDD Lowering: It is also named as Transient Voltage Collapse (TVC).In this we lower the Supply voltage of the selected memory column during write operation. We know while writing, WL is made high and BL is discharged due to which node N1 starts discharging through PGL. In case when PGL is not strong enough to oppose PUL and pull down node 1, Write failure occurs. In that case memory lowering the column supply voltage makes PUL weaker as compared to PGL. Thus successful writes occurs. Hence, numbers of assist options are available like Dual supply, Reduced bitlines, and others, but one schemes may be appropriate for one issue but it may not be necessary suitable for another. SIMULATIONS RESULTS I performed few simualtions to get better understanding about the working of the cell. Firstly, in order to find the SNM of the cell, I simulated a 6T SRAM cell, with supply voltage of 0.8mv and model SS (Slow NMOS Slow PMOS) at temperature -40. From the below graph (fig 1), we saw that the cell doesn t flip the data till it reaches 147.6mV. Going beyond that value can result in failure and cell can flip the data.

16 Fig1 After SNM, I did simulation by combining two types of assists, Negative bit line and word line under drive. In fig 2, I have used WLUD of 150mv and clearly write failure occurs. Fig 2

17 So, In order to make it right, I use negative bitline of -180mV. Keeping the WLUD at 150mv and combing it with another assist (negative bitline ), my write process was successful (fig 3) Fig 3 Thus, I analysed that while working in low voltages, it is bit tedious to run read and write simultaneously because requirement for both the operations are different. Therefore combining the assist can give desired results.

18 The Schematics of 6T SRAM cell formed in Cadence (Fig 4) Fig 4 Sizing of the transistors are kept as follows: M1: 0.2u/65nm M2: 0.2u/65nm M3:0.8u/65nm M0:0.8u/65nm M25: 1u/65nm M26: 1u/65nm M23, M27, M30 etc... remaining all are of 1u/65nm The above values depicts the width of all transistors of the bit cell. It can be clearly observed that the pull down devices are sized higher than the access transistors, this ensures high read stability. Also, pull down devices are sized weaker than the access transistors, this ensures high writeablity

19 Below is the Simulation done for Read operations. Where red line represents worldline (WL) The light pink and yellow colour line are Left and right node respectively And the blue and green line are BLB and BL respectively. This is the read operation happened successfully.

20 Now for the write operations, In the below graph,first signal (red from the top) is WL.Yellow one is BLB The below yellow(red one) is BL. The blue one is Right node, and thus the last one is the left node.

21 POWER AND LEAKAGE CURRENT As we know power consumption is a major issue of today's CMOS technology. Scaling with size results in leakage current, which makes leakages a major issue for short channel devices. There are various reasons of leakage current, such as sub threshold leakage, reverse-biased PN junctions, drain-induced barrier lowering (DIBL), gate-induced drain leakage. However, the main contributor of leakage is the sub-threshold leakage current.[9] Sub-threshold leakage is the drain-source current of a transistor when the gate-source voltage is less than the threshold voltage. More precisely, sub-threshold leakage happens when the transistor is operating in the weak inversion region. Another factor is power. Power dissipation in CMOS circuits can be categorized into two main components - dynamic and static power dissipation. Dynamic dissipation occurs due to switching transient current (referred to as short-circuit current) and charging and discharging of load capacitances (referred to as capacitive switching current). Static dissipation is due to leakage currents drawn continuously from the power supply. SUMMARY AND PROBLEMS ADDRESSED We looked into the design and analysis of Static random Access Memory (SRAMs). We also described how read /write operations are done and the role of noise margin in it. We saw how assist circuits helps to improve the stability and performance of the cell. As, SRAM continues to be a critical component in microelectronics application, we saw at low voltage, sizing affects the stability of the cell. Also Leakage is a serious problem particularly for SRAM. My main motive is to work on SRAM architecture and perform both read write, keeping the voltages as low as possible, But as we know, success of one operation results in failure of other. After understanding the theoretical working of SRAM cell, my aim was to work on the simulations. I aimed to work on how in an architecture an basics operations of read /write results keeping the load cells off and targeting only a particular cell. I came across an issue that while targeting a particular cell in a column, the other cells in the column, termed as load

22 cells still show some undesired behaviour. To deal with it, I combined two types of assists and worked on finding the point where both write and read can be done without affecting the inactive cells. Also, I am trying to simulate write failure at SF corner at very low voltage. And check if monte-carlo simulation is possible there. REFERENCES [1] Jinhui Chen Clark, L.T. Tai-Hua Chen, An Ultra-Low-Power Memory with a Subthreshold Power Supply Voltage, Solid-State Circuits, IEEE Journal, vol.41, Oct 2006, Issue: 10, pp [2] International Journal of Science, Engineering and Technology Research (IJSETR), Volume 4, Issue 8, August ISSN: All Rights Reserved 2015 IJSETR LOW POWER SRAM CELL OF LEAKAGE CURRENT AND LEAKAGE POWER REDUCTION K.VENUGOPAL P.SIREESH BABU [3]B. Mohammad, P. Dadabhoy, K. Lin, and P. Bassett, Comparative Study of Current Mode and Voltage Mode Sense Amplifier Used for 28nm SRAM, in Microelectronics (ICM), th International Conference on, Dec 2012, pp. 1 [4]E. Grossar Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies, IEEE J.Solid-State Circuits,vol.41,no.11,pp ,Nov [5] E. Seevinck et al., Static-Noise Margin Analysis of MOS SRAM Cells, IEEE J.Solid-State Circuits, vol.sc-22, no.5 pp , Oct [6]B. Calhoun and A. Chandrakasan, Analyzing static noise margin for subthreshold SRAM in 65 nm CMOS, in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2005, pp [7]Prajna Mishra, Eugene John and Wei-Ming Lin Static Noise Margin and Power Dissipation Analysis of various SRAM Topologies IEEE 56th International Midest Symposium on Circuits and Systems (MWSCAS), pp , 2013 [8] R. W. Mann, J. Wang, S. Nalam, S. Khanna, G. Braceras, H. Pilo, and B. H. Calhoun, Impact of circuit assist methods on margin and performance in 6T SRAM, Solid State Electron., vol. 54, no. 11, pp , Nov [9]Birla, S.,Shukla,N. Kr., Singh,R.K, and Pattanaik,M.,2010 "Leakage Current Reduction in 6T Single Cell SRAM at 90nm Technology, in Proceedings of IEEE International Conference on Advances in Computer Engineering, pp

23