A Write-Back-Free 2T1D Embedded. a Dual-Row-Access Low Power Mode.

Transcription

1 A Write-Back-Free 2T1D Embedded DRAM with Local Voltage Sensing and a Dual-Row-Access Low Power Mode Wei Zhang, Ki Chul Chun, Chris H. Kim University of Minnesota, Minneapolis, MN zhang758@umn.edu

2 Outline Introduction to Gain Cell EDRAM Proposed EDRAM Techniques Write-Back-Free Read Operation Local Sense Amplifier Architecture Dual-Row Access Mode 65nm EDRAM Chip Measurements Conclusion 2

3 Embedded Memory Options 6T SRAM 1T1C edram 2T gain cell edram 3T gain cell edram WL WL BL RBL RBL Cell Schematic BL BLB WL VP WBL WBL (1) Reported cell size (ratio) (2) Redrawn cell size (ratio) Low-VDD margin Process 0.46x1.24= µm 2 (1X) 0.575x2.05= 1.179µm 2 (1X) Poor (ratioed) Logic compatible 0.23x0.55= µm 2 (0.22X) 0.45x0.545= 0.245µm 2 (0.21X) Poor (destructive read) Trench cap. + thick TOX access TR 0.475x0.58= µm 2 (0.48X) 0.48x0.925= 0.444µm 2 (0.38X) Good (non-ratioed, gain function) Storage cap. irrelevant <10fF ~1fF Logic compatible Retention time % Random cycle (2) 1ns 2ns 2ns Static ti power 1.0X 0.2X - (1) All designs are in 65nm. (2) Based on the same 65nm low power CMOS process x1.015 = 0.528μm 2 (0.45X) Good (non-ratioed, gain function) ~1fF Logic compatible (simulation) 2-4ns - 3

4 Retention Time of Gain Cells Gain cells have very small storage capacitance Retention time varies exponentially with PVT Longer retention time guarantees higher read performance and lower refresh power 4

5 Novel Gain Cells: 2T Asym. and 2T1C [1] K. Chun, VLSI Symp., 2010 [2] K. Chun, ISSCC T asymmetric gain cell for performance boost 2T1C gain cell for true logic compatibility PCOU coupling increases read current and helps restore data 0 5

6 Unexplored Advantage of Gain Cell EDRAM: Non-Destructive Read Destructive Read Non-destructive Read 1T1C DRAM 3T Gain Cell BL WL cell WBL WWL cell RBL RWL Volta age Volta age 6

7 Impact of Write-Back-Free Read 7

8 Impact of Write-Back-Free Read % 0.01% 0.1% 1% 10% No adverse effect on data retention Negligible data 1 change & improved data 0 Experimental data required at practical access rates 8

9 Read Cycle Time w/o Write-back WBL Drive Precharge +70.6% Write-Back BL-SA +43.4% WL- BL (6σ) IO This work: +5.3% kb, 1.1V, 65nm, 85ºC, 6σ delay 0.0 6T SRAM 2T1D 2T1D 2T1D conv. no WB no WB, local SA Non-destructive read allows write-back-free operation Write-back w/ WBL switching: ~30% of the cycle time Reduces write-back power during read operations 9

10 Evaluation Vehicle: 2T1D Gain Cell Variant of 2T1C gain cell Individual N-type coupling diode for minimal distrub Preferential coupling [3] during read MOS cap is higher when diode transistor is on [3] K. Chun, VLSI Symp.,

11 2T1D Cell Preferential Coupling Effect Data 1 receives stronger coupling Higher read current and larger sensing window 11

12 Read Disturbance in 2T Based Cells Cell<0> Cell<1> Cell<255> I READ I LEAK I LEAK RBL (VDD- ) 0.85V 1.1V 1.1V1V VDD WBL (VDD) ~200mV RBL w/ disturbance VD DD WWL<0> Selec ctd (GN ND) RWL<0> VD DD Unselec ctd (VD DD) VD DD Unselec ctd (VD D) RBL w/o disturbance Worst case: read current vs. (disturbing current x (N-1)), N = cell per RBL Voltage sensing Disturb current from adjacent data 1 cells sharing RBL Current sensing Large area and susceptible to PVT variation 12

13 Read Disturbance Mitigation Conventional Unselected (X255) VDD GND VDD 0.85V VDD 1.1V RBL (VDD- ) Scheme PCOU coupling Sensing margin improvement +20mV READ LEAK WBL (VDD) Local-SA architecture 64 cells per LRBL Regulated WBL +64mV +178mV This Work VDD PCOU GND 0.95V READ Unselected VDD VDD 0.9V LEAK (X63) Local RBL (VDD- ) Regulated WBL (VDD-0.2V) PCOU coupling increases read current Regulated WBL reduces disturbing current Local-SA scheme reduces number of disturbing cells Read current vs. (disturbing current x ( N -1)) 13

14 Architecture w/ Local SA 64 Cells per Local RBL 4 LSAs per Global RBL GRBL<0> LRBL<0> LSA LRBL<3> LSA WBL Global l Sense Amp Voltage S/A: 4.5% area overhead (compare with 6.4% for current S/A) 3.5% area overhead Dummy Averaging WWL RWL L_Precharge GRBLB<0> LRBL 0V GRBL<i> GRBLB<1> GRBLB<i> 0V GRBLB<2> REF WBL LSA_EN PCOU 0V GRBLB<126> GRBLB<127> LSA increases total memory area by 1.6% 1.9% area savings compared to current SA 14

15 Dual-Row Access Scheme WL0 PCOU0 RWL0 WL63 PCOU63 RWL63 WL64 PCOU64 RWL64 WL127 PCOU12 27 RWL127 Simultaneously refresh two rows storing duplicate data when <50% of the array block is utilized Weak cells repaired by statistical averaging with stronger cells 15

16 Retention Time Measurements Failure Pe ercentile (% %) Bit tline # Failure percentile no significant difference across access rates 1.0ns read cycle time at 1.1V w/ 325 μsec retention time 16

17 Static Power Measurements 65nm LP, 85 C 1E4 1E3 1E2 1E1 SRAM Leakage 2T1D Refresh Power Consumption (μw/ 1Mb) 6T SRAM (0.6V Retentionn Voltage) 2T1D Full Array 2T1D Half Array 2T1D 2-row Current Consumption (μa/mb) Retention Voltage (V) 23.9% lower power than a power-gated 6T SRAM with a data retention voltage of 0.6V Additional 27.8% power saving with dual-row access mode 17

18 EDRAM Test Chip Summary 32 kb 2T1D Array LSA Row Dec. 32 kb 2T1D Array LSA Row Dec. Test Interface 322.8µm Process Main feature Cell size Array size 99.9% retention time Rd. Cycle Wr./Ref. Cycle Cell Availability Static Power 65nm LP CMOS Write-back-free read 57% of 6T SRAM 64 kb (512WLx128BL) 1.1V, 85ºC 1.1V, 85ºC 1.1V, 85ºC 1Mb, 1.1V, 85ºC, 325 μsec refresh V, 85ºC, 325 μsec refresh 1.0ns read cycle time at a 325 μsec, 99.9% retention time condition under 1.1V supply First demonstration of a gain cell edram without write-back operation 18

19 Conclusions Gain cell edram as an alternative for SRAM ~2X higher bit cell density, logic compatible Separate read and write paths Non-destructive read Proposed gain cell edram Write-back-free read operation Voltage sensing for 2T-based gain cells Dual-row access low power mode A 1.1V, 1V 65nm edram chip demonstrated 1.0ns read cycle time, 325 μsec 99.9% retention time 1 st experimental results showing write-back-free read 23.9% power savings compared to 6T SRAM 19