Monitoring System for Optical Fiber Network Security

Transcription

1 University of Manitoba Department of Electrical & Computer Engineering ECE 4600 Group Design Project Project Proposal Monitoring System for Optical Fiber Network Security by Group 04 Alexander Luft Katrina Mae Soriano Pawanpreet K Sidhu Daniel Tweed Lucy Apuugum Academic Supervisor Prof. Sherif Sherif, Ph.D., P.Eng. Industry Supervisors Michael Brown, P.Eng. Norscan Instruments Ltd. Yolande Cates, P.Eng. Norscan Instruments Ltd. Date of Submission September 26, 2014 Copyright 2014 Alexander Luft, Daniel Tweed, Katrina Mae Soriano, Lucy Apuugum, Pawanpreet K Sidhu

2 CONTENTS Contents 1 Introduction Project Details Data Acquisition Module Data Storage Module Bus Control Module Hardware Abstraction Layer Graphical User Interface Specifications Division of Labour Gantt Chart Budget Conclusions References 9 - i -

3 LIST OF FIGURES List of Figures 1 Block diagram of the complete optical monitoring system developed by Norscan [1]. 1 2 Block diagram of the hardware components of the optical monitoring unit [1] Gantt chart for the optical monitoring unit project List of Tables 1 System Specifications Division of Tasks Project Budget ii -

4 1 Introduction 1 Introduction Optical fiber is becoming the preferred data transmission medium due to optical fiber s greater capacity (bandwidth), lower risk of loss, and relative immunity to common interference sources, when compared to copper wires [2]. One of the challenges encountered by data communication technologies is the risk of security breaches. With the growth in optical fiber networks, there is a growing need to secure these networks against tampering and data interception. The industry sponsor of this project, Norscan Instruments Ltd., has developed an innovative technique to detect disturbances to optical fiber lines, which could indicate malicious tampering [1]. The polarization state of the beam in a monitored fiber optic line is continuously modulated between orthogonal states, while the polarization state of the received beam is monitored for unexpected changes which could indicate that the line is being tampered with. The existing implementation of the monitoring system, shown in Figure 1 below, uses LabVIEW, and it is desired that it be redesigned as a custom embedded system. Fig. 1: Block diagram of the complete optical monitoring system developed by Norscan [1]. This project will implement the shaded components in Figure 1 in hardware and develop the required software for the main processing module and user interface. This design will make use of the BeagleBone Black, an ARM based single-board computer, and the LOGi-Bone FPGA Cape for development. Software will run in a Linux environment, and hardware will be implemented in the FPGA as modules which can be developed, tested, and operated independently, so as to facilitate parallel development and greater re-usability. The user interface of the processing module will allow for the control of the system and display the raw data obtained by the system over time. As per the sponsors request, where possible, off-the-shelf components will be used to shorten development time and provide for easier future implementation as a custom system for production

5 2 Project Details 2 Project Details The project development will be decomposed into three hardware modules and two software modules, as follows: Data Acquisition (DAQ), Data Storage, Bus Control, Hardware Abstraction Layer (HAL), and a Graphical User Interface (GUI). The development will also be done in three phases: Preliminary Work, Component Design and Testing, and Module Integration and Testing. All modules will developed in parallel so they can be designed, integrated, and tested as quickly as possible. FPGA development will be done in Verilog HDL and using the Xilinx ISE WebPACK software. A packet decoder will be developed for use by hardware modules to create packets for outgoing data and decode the received packets. A block diagram of the hardware modules to be developed is shown in the Figure 2 below. Fig. 2: Block diagram of the hardware components of the optical monitoring unit [1]. 2.1 Data Acquisition Module The DAQ will be responsible for interfacing the LOGi-Bone to the ADC, obtaining data and sending the data to the data storage module for storage in SDRAM. The DAQ will be developed on the LOGi-Bone cape and will implement both a wishbone slave to respond to commands from the BeagleBone Black, and a wishbone master to send data to the data storage module. The DAQ will control the external ADC, initiate the transmission of data, and implement a FIFO for locally storing acquired samples

6 2 Project Details 2.2 Data Storage Module The Data Storage Module will implement a wishbone slave to respond to read and write requests from master devices. The module will implement an SDRAM controller to handle read and writes to the external SDRAM. The 16-bit SDRAM controller from Opercores.org is of potential to use in this project as it presents essential features required by the project, such as the wishbone compatibility [3]. The data storage module will also implement logic required to track the read/write pointers, determine memory space conditions (i.e. overwrite conditions), and set flags. 2.3 Bus Control Module The Bus Control Module provides both the interface between the general-purpose memory controller (GPMC) on the BeagleBone Black and the LOGi-Bone s on-board FPGA as well as the Wishbone bus interconnections, bus control, and arbitration facilities. The Syscon shown in Figure 2 will provide the base system clock and reset signals for all of the FPGA modules [4]. The Intercon will implement the standard master/slave signals to connect two masters to two slaves, generate control packets, manage a cross-bar bus to provide the necessary connections between Wishbone masters and slaves and perform address decoding to make the necessary connections [5]. The GPMC-Wishbone Interface will implement the LOGi-Wishbone interface for the BeagleBone Black, provided by ValentFX [6]. 2.4 Hardware Abstraction Layer The HAL provides an Application Program Interface to the GUI. This will allow the GUI to interact with the hardware on the LOGi-Bone without directly interacting with the physical layer pins and signals. Access will be provided through a user-space driver interacting with a kernel-space driver. The kernel-space driver, provided by ValentFX, is specifically designed for interfacing the BeagleBone Board and the LOGi-Bone FGPA through the BeagleBone Black s GPMC [7]. 2.5 Graphical User Interface The GUI will give the user options to start and stop data collection. When data is being collected, a graph will display the raw data in voltages over time. The interface will use a Linux standard interprocess communication (IPC) method called pipes to communicate with the HAL. The GUI will be developed with the Qt UI framework using C

7 3 Specifications 3 Specifications The DAQ, Data Storage, and Bus Control will be implemented on the LOGi-Bone FPGA, with each of the DAQ and Data Control modules mapped to 1 kb of addresses within the LOGi-Bone, to allow mapping up to 1024 unique commands as memory accesses. System specifications are provided on Table 1 below. Table 1: System Specifications Modules Feature Value or Range Data Acquisition Sampling Rate 50 ksps Interface to ADC SPI Data Storage Module Data Bus Width 16 bits SDRAM Memory Size 32K Bus Control Module System Clock Min. 133 MHz Bus Width 16 bits Master Reset Available from HW and SW Wishbone Bus Data Rate Min. 250 MB/s Additional Signals Provided Clock, Reset, Clear to Send, to Other Modules Request to Send, Retry Graphical User Interface Controls Available Start, Stop Data Display Plot voltages over time, scalable Communication Standard Linux standard IPC method (pipes) 4 Division of Labour The project will be decomposed into five modules, with each team member being lead on one module, and secondary on at least one other module. This structure will allow each portion of the design able to be developed and tested independently. In addition, this cross-responsibility will allow greater understanding by each team member of where their modules fit in and work with the overall project as the development progresses. A breakdown of tasks and responsibilities is shown in Table 3 on the next page. The Gantt chart, Figure 3 on page 6, provides a complete breakdown of all tasks

8 5 Gantt Chart Table 2: Division of Tasks Tasks Preliminary Work Design Packet Decoder DAQ Components Data Storage Components Bus Control Components Implement GPMC-Wishbone Interface Implement Wishbone Bus Modules Implement HW Components in Verilog HAL Components Design of the API Implement API functions Implement the LOGi-Bone driver GUI Components Design GUI mock-ups Get Supervisor Approval of GUI Layout Implement Code for GUI Component Integration and Testing Module Integration and Testing Integrate Modules and Testing Finalize System and Obtain Sign-off Individual in charge All Pawan, Katrina, Daniel Pawan Katrina Daniel Daniel Pawan, Katrina, Daniel Pawan, Katrina, Daniel Lucy Lucy Lucy Lucy Alex Alex Alex Alex All All All All 5 Gantt Chart A Gantt chart is used in this project as a schedule managing tool. It maps the progress of the group, sets internal deadlines for milestones and deliverables of the team, and provides feedback to the performance of the group in terms of time management. The Gantt chart, shown in Figure 3 on the next page, will be updated as the group progresses towards completion of the project to ensure that the group stays on schedule

9 5 Gantt Chart Fig. 3: Gantt chart for the optical monitoring unit project

10 6 Budget 6 Budget The budget for the project is $ All of the components listed on the table below are being provided by the industry sponsor of this project, Norscan Instruments, Ltd. Table 3: Project Budget Item Part Number Supplier Unit Cost Quantity Total BeagleBone Black BBB-BLK-000 Circuitco $ $ LOGi-Bone LOGi-Bone ValentFX $ $ V 2.5A AC/DC power supply 16bit 6CH 250KSPS simultaneous sampling IC regulator boost and inverting +/-12V EPSA050250U-P5P- EJ AD7656ABSTZ Analog Devices LT3582EUD-12#PBF CUI $ $66.40 Linear Technology $ $30.00 $ $5.75 Inductor 6.8uH 540mA LQH32CN6R8M53L Murata $ $0.84 Schottky diode 40V 0.5A B0540WS-7 Diodes Inc $ $1.20 Ceramic capacitor 4.7uF 10V X7R Ceramic capacitor 4.7uF 16V X7R Ceramic capacitor 10uF 16V X7R Ceramic capacitor 1uF 16V X7R Ceramic capacitor 10nF 50V X7R C2012X7R1A475M 125AC CGA4J3X7R1C475 K125AB C3216X7R1C106M 160AC C2012X7R1C105K 125AA C0805C103K5RAC TU TDK $ $0.29 TDK $ $0.41 TDK $ $0.41 TDK $ $0.16 Kemet $ $0.24 2x socket SSQ T-D Samtec $ $ position header TE connectivity 10 position header TE connectivity $ $1.09 $ $0.75 Transimpedance board TIA circuit Norscan $ $65.00 SD card N/A Kingston $ $60.55 Total: $

11 7 Conclusions 7 Conclusions The optical monitoring unit will enhance the security of fiber optic networks. The implementation of the unit as a custom embedded system will further Norscan Industries development towards a deployable product. The main system modules are the data acquisition, data storage, and bus control modules, which will be implemented as custom modules on an FPGA and interface the data source with the software modules, the hardware abstraction layer and user interface, running on the BeagleBone Black. The total budget for this project is $ CAD, with all components provided by Norscan. We have decomposed the project into separate modules, designed a work breakdown which emphasize cross-responsibility and redundancy, and established tasks and milestones to ensure that the project will be completed on time

12 REFERENCES References [1] M. Brown, Optical monitoring unit: Ece 4600 group design project, Norscan Instruments, Ltd., Tech. Rep. Revision 2, May [2] J. Kurose and K. Ross, Computer Networking: A Top-Down Approach. Pearson Education, ch. Computer Networks and the Internet, p. 20. [3] Opencores.org, 8/16/32 bit sdram controller :: Overview, ctrl,overview, June 2014, accessed: [4], Wishbone b4: Wishbone system-on-chip (soc) interconnection architecture for portable ip cores, b4.pdf, 2010, accessed: [5] J. Piat and M. Jones, Wishbone intercon, logi-hard, blob/master/hdl/wishbone/wishbone intercon.vhd, 2013, accessed: [6], Gpmc-wishbone wrapper, logi-hard, master/hdl/wishbone/gpmc wishbone wrapper.vhd, 2013, accessed: [7] ValentFX, Logi-bone user guide, valentfx.com/wiki/index.php?title=logi-bone User Guide, accessed: