Design Development and Implementation of SPI

Transcription

1 MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp Design Development and Implementation of SPI A. Sirisha Kurnool (DT), A.P, INDIA M. Sravanthi Kurnool (DT), A.P. INDIA N. Sreenivasa Rao Kurnool (DT), A.P. INDIA ABSTRACT There are many communication protocols for both short and long distance communication purpose such as ETHERNET, USB, SATA, PCI-EXPRESS are used for long distance and I2C and SPI are used for short distance communications. SPI is a serial interface protocol, compared to other protocols, it has high transmission speed, simple to use and little pins advantages. The four interfaces are required by standard SPI protocol at least. Usually, the devices which based on SPI protocol are divided into master device and slave-device for transmitting the data. The chip select signal and clock signal have be generated by the master-device when the data exchange has been processed. SPI is often considered as the little communication protocol which is used for ON-Board communication. Although the literature on SPI protocol is so extensive and the topic is so old (early 1980), to the best of the authors knowledge there is no comprehensive analysis of SPI problem. By comprehensive analysis, we mean a treatment that start from Motorola s V03.06 SPI bus specifications and goes down to the actual ASIC/FPGA implementation, discussing all relevant architectural aspects and providing all design details. In our attempt to implement universal SPI IP cores according to the design- reuse methodology, we first made a market study of an important number of recent commercial SPI devices (datasheets) from different vendors to look at the requirements and what features are to be included to satisfy modern ASIC/SoC applications. 1. INTRODUCTION: SPI The Serial Peripheral Interface (SPI) protocol is asynchronous serial data standard, primarily used to allow a microprocessor to communicate with other microprocessors or ICs such as memories, liquid crystal diodes (LCD), analog-to-digital converter subsystems, etc. The SPI is a very simple synchronous serial data, master/slave protocol based on four lines: Clock Line (SCLK) Serial Output (MOSI) Serial Input (MISO) Slave Select (SS) 1.1 SPI Protocol Fig. 2: SPI with Single Master and Single Slave Fig. 1: Block Diagram SPI Signal Descriptions Master In Slave Out (MISO): The MISO line is configured as

2 MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp an input in a master device and as an output in a slave device. It is one of the two lines that transfer serial data in one direction, alongwith the most significant bit sent first. The MISO line of a slave device is placed in the high-impedance state if the slave is not selected. Master Out Slave In (MOSI): The MOSI line is configured as output in a master device and as an input in a slave device. It is one of the two lines that transfer serial data in one direction, with the most significant bit sent first. Serial Clock (SCK): The serial clock is used to synchronize data movement both in and out of the device through its MOSI and MISO lines. The Master and Slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Since SCK is generated by the master device, this line becomes an input on a slave device. Slave Select (SS_bar): The slave select input line is used to select a slave device. It has to be low prior to data transactions and must stay low for the duration of the transaction. SPI Data Transmission: The SPI has four modes of operation, 0 through 3. These modes essentially control the way data is clocked in or out of an SPI device. 2. PGA DESIGN FLOW 2.1 Design Flow The ISE design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. This section describes what to do during each step. For additional details on each design step, click on a link below the following figure. Design Entry Fig. 4: FPGA Design Flow Create an ISE project as follows: 1. Create a project. 2. Create files and add them to your project, including a user constraints (UCF) file. 3. Add any existing files to your project. Assign constraints such as timing constraints, pin assignments, and area constraints. Fig. 3: SPI Bus Modes The configuration is done by two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock. The clock phase (CPHA) control bit selects one of the two fundamentally different transfer formats. To ensure a proper communication between master and slave both devices have to run in the same mode. This can require a reconfiguration of the master to match the requirements of different peripheral slaves. SPI is a Synchronous data transmission, clock plays important role in this Communication. For describing the clock information we have two flags called CPOL and CPHA in SPI Control Register. The CPOL clock polarity control bit specifies an active high or low clock. The CPHA clock phase control bit selects one of two different transmission formats. 3. DESIGN OF SPI 3.1 Master Fig. 5: SPI Master

3 MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp Features 3- to 16-bit data width Four SPI operating modes Bit rate up to 9 Mbps 3.2 Slave Features 2 to 16-bit data width 4 SPI modes Data rates to 33 Mb/s General Description The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI slave device. In addition to the standard 8-bit word length, the SPI Master supports a configurable 3- to 16-bit word length for communicating with non standard SPI word lengths. SPI signals include the standard Serial Clock (SCLK), Master In Slave Out (MISO), Master Out Slave In (MOSI), bidirectional Serial Data (SDAT), and Slave Select (SS) When to Use the SPI Master? SPI Master Component can be used any time the PSoC device must interface with one or more SPI slave devices. In addition to SPI slave labeled devices, the SPI Master can be used with many devices implementing a shift-register-type serial interface. SPI Slave component can be used in instances in which the PSoC device must communicate with an SPI master device. The Shift Register component should be used in situations where its lowlevel flexibility provides hardware capabilities not available in the SPI Master component Input/Output Connections This section describes the various input and output connections for the SPI component. An asterisk (*) in the list of I/Os indicates that the I/O may be hidden on the symbol under the conditions listed in the description of that I/O General Description The SPI Slave provides an industry-standard 4-wire slave SPI interface and 3-wire (or bidirectional) SPI mode. The interface supports 4 SPI operating modes, allowing interface with any SPI master device. In addition to the standard 8-bit interface, the SPI Slave supports a configurable 2- to 16-bit interface for interfacing to nonstandard SPI word lengths. SPI signals include the standard SCLK, MISO + MOSI (or SDAT) pins and Slave Select (SS) signal When to use the SPI Slave? The SPI Slave component should be used any time the PSOC device is required to interface with a SPI Master device. In addition to SPI Master labeled devices the SPI Slave can be used with many devices implementing a shift register type interface. The SPI Master component should be used in instances requiring the PSOC device to interface with a SPI Slave device. The Shift Register component should be used in situations where its low level flexibility provides hardware capabilities not available in the SPI Slave component Input/output Connections This section describes the various input and output connections for the SPI. An asterisk (*) in the list of I/O indicates that the I/O may be hidden on the symbol under the conditions listed in the description of that I/O. 3.3 ON ChIP PERIPhERAL BUS Fig. 7: On Chip Peripheral Bus Fig. 6: Slave Block Diagram OPB is developed by IBM. It is something like PCI on chip. It is an On-Chip bus that provides link between the processor

4 MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp core and other peripherals. OPB is fully synchronous and nonmultiplexed. It supports 8-bit, 16-bit, 32-bit, 64-bit slaves and 32-bit, 64-bit masters. The single cycle transfer of data takes place between OPB bus master and OPB slaves. The transaction carried out is Pipelined transaction. There are separate 32-bit read write buses and it has up to 64 bit address bus. It is the most used Peripheral bus for slower devices. 4.1 Slave: 3.4 MASTER AND SLAvE COMMUNICATION The SPI protocol basically defines a bus with four wires (four signals) and a common ground. There is one master device controlling the activity on the bus, and one slave device. The slave is active only when one of the signals, Slave Select (SS) enables it. This signal is always provided by the master. There can be more than one slave connected to the SPI bus, but each slave requires its own Slave Select signal, see Fig. 1. The data gets transferred serially bit by bit. There are basically two signals to carry information, one from master to slave (MOSI, Master Output Slave Input, driven by master), and one for the opposite direction (MISO, Master Input Slave Output, driven by slave). The last signal SCLK (Serial CLocK) assures the time synchronization between master and slave, and is always driven by master. There are streamlined versions of the SPI bus using only one signal to transfer data, but the direction of data must be reversed on request; we will not use this kind of data transfer. Fig. 9: RTL Schematic of Slave Fig. 10: Output of Slave 4.2 MASTER Fig. 8: Master to Multiple Slave Communication 4. SOFTWARE USED For Synthesis and Implementation: Xilinx ISE (Integrated Software Environment) is a software tool produced by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize ( compile ) their designs, perform timing analysis, examine RTL diagrams, simulate a design s reaction to different stimuli, and configure the target device with the programmer. Starting the ISE Software To start ISE, double-click the desktop icon, or start ISE from the Start menu by selecting: Fig. 11: RTL Schematic of Master

5 MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp ADvANTAGES AND USES Fast and easy. Fast for point-to-point connections. Easily allows streaming/constant data inflow. No addressing/simple to implement. Everyone supports it. It supports all four modes. The Master and Slave are independent of each other. It can be operated in Simplex, Duplex and Full Duplex. It can be programmed at any frequency and at any data width. Uses: Some Serial Encoders/Decoders, Converters, Serial LCDs, Sensors, etc. Pre-SPI serial devices PPC implements SPI well. The bus of choice for communicating with small peripherals. 4.3 FINAL OUTPUT Fig. 12: Output of Master Fig. 13: Output of OPB 6. CONCLUSION The Design of Serial Peripheral Interface (SPI) with Single Master and Single Slave configuration has been done successfully showing that it operates in Simplex Mode. This SPI master is a flexible programmable logic component that accommodates communication with a variety of slaves via a single parallel interface. It allows communication with a user specified number of slaves, which may require independent SPI modes, data widths, and serial clock speeds. Thus, Designed SPI Protocol is used in Real Time application of a SoC (System on chip) in order to communicate with the PPC 440 Processor and other peripherals which is applicable for present day Avionics Systems in Defense. 7. FUTURE SCOPE The capabilities of a new flash memory interface from ST Microelectronics, which uses a Serial Peripheral Interface to access serially, organized flash non-volatile memory devices over what it refers to as the SPI Flash Interface. SPI is now ubiquitous in embedded designs, an integral element in microcontrollers and FPGAs, and in applications in instrument panel clusters, digitally controlled potentiometers, M2M applications, industrial controller area networks (CAN), temperature measurement and robotics. REFERENCES Fig. 14: Final Output 1. SPI Block Guide V03.06, Free scale Semiconductor. 2. SPI Adapter with support of custom serial protocols, Byte Paradigm. 3. Tulwartechnologies offers FPGA designservices. Tulwartechnologies.com Retrieved McConnel, Toni, EETimes, ESC - Xilinx All Programmable System on a Chip combines best of serial and parallel processing. April 28, Retrieved February 14, Clock Generation, Doulos, Retrieved 22 December IEEE Standard VHDL Language Reference Manual doi: /ieeestd ISBN