CR5M: A Mirroring-Powered Channel-RAID5 Architecture for An SSD

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1 CR5M: A Mirroring-Powered Channel-RAID5 Architecture for An SSD Yu Wang 1, Wei Wang 2, Tao Xie 2, Wen Pan 1, Yanyan Gao 1, Yiming Ouyang 1, 1 Hefei University of Technology 2 San Diego State University The 30th International Conference on Massive Storage Systems and Technology (MSST 2014), California, 2014

2 Outline Introduction Design and implementation Experimental results Conclusions

3 Introduction of NAND Flash High performance Low-power consumption High shock resistance Small physical size

4 Introduction of NAND Flash Increasing Flash Capacity Density Smaller geometries of flash memory cell 45nm~20nm More bits each cell store SLC~TLC Decreasing Endurance and Reliability SLC ~100k P/E cycles MLC ~10k P/E cycles

5 Introduction of NAND Flash Flash Memory Errors Transient (or soft) Errors Permanent (or hard) Errors ECC (Error Correction Code) Per 256 to 512 bytes, ECC typically can Detect two bit errors Correct one bit error Errors beyond that range may be unrecoverable.

6 Introduction of NAND Flash ECC are incapable of correcting these errors: Word line errors Block or die errors Multiple-bit transient errors

7 RAID RAID has successfully been implemented in HDD arrays SSD arrays Im and Shin proposed a Delayed Partial Parity Scheme for Reliable and High-Performance Flash Memory SSD (MSST2010) Kadav et al. presented Diff-RAID, a new RAID variant that distributes parity unevenly across SSDs to create age disparities within arrays (ACM Transactions on Storage 2010) HDD+SSD hybrid arrays

8 Channel-RAID (CR) - Requirement Cases where only one SSD can be deployed yet data reliability is critical. Such as: a) Wireless Healthcare System b) Mobile Military Application

9 Channel-RAID (CR) - Feasibility The multi-channel structure provides an opportunity to implement RAID into a single SSD CR1 (Channel-RAID1) CR4 (Channel-RAID4) CR5 (Channel-RAID5)

10 CR5 (Channel-RAID5) Striping size is adjusted to (N-1) page size N means the number of channels.

11 CR5 (Channel-RAID5) Full-Stripe Write: no extra read operation Partial-Stripe Write RMW (Read-Modify-Write): reads the old data of the updates and its associated parity. RCW (Read-Reconstruct-Write): reads the rest part of the stripe (i.e., the data that are not going to be updated). The method whose pre-read operation number is less will be selected.

12 Limitations of CR5 SSD Decreased Lifetime Degraded Performance Vulnerability

13 CR5M (Mirroring-Powered Channel-RAID5) The key feature: an extra chip is introduced to each channel serve as a mirroring chip. Host Interface SSD Controller Channel 0 Channel 1 Channel 2 Channel 3 Chip 0 Chip 1 Chip 2 Chip 3 PPN PPN PPN PPN Chip 4 PPN Chip 5 Chip 6 Chip 7 Chip 8 Chip 9 Chip 10 Chip 11 Chip 12 Chip 13 Chip 14 Chip 15 Chip 16 Chip 17 Chip 18 Chip 19 0 D 0 40 D 3 80 D P D 1 D 4 P 2 D 9 D 2 P 1 D 7 D 10 P 0 D 5 D 8 D 11 1 D D P D P 4 D 16 D 19 D 12 D 13 D 20 P 5 D 12 D 14 D 17 P 6 D Mirroring Chip Mirroring Chip Mirroring Chip Mirroring Chip Stripe mapping table D : User Dat a Stripe 0 Ch0:C0:D 0 Ch1:C5:D 1 Ch2:C10:D 2 Ch3:C15:P 0 P : Pairty Data Stripe 1 Ch0:C1:D 3 ' Ch1:C6:D 4 Ch3:C16:D 5 Ch2:C11:P 1 D : Invalided Data

14 MW (Mirroring Write) MW concurrently writes both the original update and a copy of it onto its destination chip and the mirroring chip. D 3 ' Comes Host Interface SSD Controller Channel 0 Channel 1 Channel 2 Channel 3 Chip 0 Chip 1 Chip 2 Chip 3 PPN PPN PPN PPN Chip 4 PPN Chip 5 Chip 6 Chip 7 Chip 8 Chip 9 Chip 10 Chip 11 Chip 12 Chip 13 Chip 14 Chip 15 Chip 16 Chip 17 Chip 18 Chip 19 0 D 0 40 D 3 80 D P D 3 ' D 1 D 4 P 2 D 9 D 2 P 1 D 7 D 10 P 0 D 5 D 8 D 11 1 D D P D P 4 D 16 D 19 D 12 D 13 D 20 P 5 D 12 D 14 D 17 P 6 D D 3 ' Mirroring Chip Mirroring Chip Mirroring Chip Mirroring Chip Stripe mapping table D : User Dat a Stripe 0 Ch0:C0:D 0 Ch1:C5:D 1 Ch2:C10:D 2 Ch3:C15:P 0 P : Pairty Data Stripe 1 Ch0:C1:D 3 ' Ch1:C6:D 4 Ch3:C16:D 5 Ch2:C11:P 1 D : Invalided Data

15 Revised Mapping Table Mirroring Address (MA) is appended to each entry. Its value tells the existence of mirroring data for current entry.

16 Workflow of CR5M

17 Experimental Setup The Characteristics of Traces Trace Name Write Ratio (%) Ave.Size (KB) Access Rate (req/sec.) Duration (mins.) Financial Radius ATTO Build Exchange The Varied Experiment Parameters Conf. Pure SSD CR1 CR4 & CR5 CR5M SSD1 4cl-6cp 8cl-6cp 4cl-6cp 4cl-7cp SSD2 6cl-4cp 12cl-4cp 6cl-4cp 6cl-5cp SSD3 8cl-3cp 16cl-3cp 8cl-3cp 8cl-4cp cl: the channel number in an SSD cp: the chip number on each channel

18 Performance Evaluation on SSD1 27% 3.8% 0% 1.7% 0.6% 3% 0.7% 6.5% 23.3% 10.2% 3.6% 22.6% 6% 21.5% 5.4%

19 Performance Evaluation on SSD2 1.2% 0.3% 0.1% 1.4% 1.5% 27.2% 8.2% 6.3% 23% 13.4% 7.8% 21.2% 5.8% 21.2% 7.4%

20 Performance Evaluation on SSD3 0.3% 0.5% 0% 1.2% 1.9% 1.9% 27.6% 14.6% 25.9% 9% 1.7% 25.8% 8.5% 19.7% 8.6%

21 The Impact Of Write Percentage CR5M outperforms CR5 by up to 24.1%.

22 The Impact Of Average Request Size CR5M outperforms CR5 by up to 31.7%.

23 Parity Pre-Read Overhead On average CR5M reduces the number of pre-reads by 56%.

24 Wear-Leveling Evaluation Number of writes (X10 4 ) Fin1 CR5 CR5M SSD1 SSD2 SSD3 Build Exchange ATTO Radius9 Fin1 Build Exchange ATTO Radius9 CR5M can reduce the number of writes per channel by 14% compared with CR5. Fin1 Build Exchange ATTO Radius9

25 Conclusions ECC scheme has its own capacity limitation, above which it can no longer work. We implement several common RAID structures in the channel level of a single SSD to understand their impact on an SSD s performance. We propose a new data redundancy architecture for a single SSD called CR5M We largely extend the validated SSD simulator SSDSim Experimental results demonstrate that CR5M outperforms CR5 by up to 25.8%.

26 Future Work We will implement and study the channel- RAID architecture on a hardware evaluation board.

27 Acknowledgments This work is sponsored in part by the U.S. National Science Foundation under grant CNS- (CAREER) and Key Technologies R&D Program of Anhui Province (China)

28 Thank you!