High-Efficiency SSD for Reliable Data Storage Systems

Transcription

1 High-Efficiency SSD for Reliable Data Storage Systems -Improving endurance and data reliability of next generation flash in embedded applications Jeff Yang Principle engineer Silicon Motion, Inc. Flash Memory Summit 2

2 Agenda The challenges of TLC flash in embedded applications The methods to overcome the retention and endurance disturbance Soft-decoding for larger noise Impact of soft-decoding Endurance enhancement of TLC flash Conclusion Flash Memory Summit 2 2

3 The Challenges of TLC Flash in Embedded Applications Flash Memory Summit 2 3

4 Read Retry Interface Mechanism 3 steps left / 3 steps right Total 7 steps (including the original read) The Read Retry Interface is typical in TLC flash. This interface can be used for:. State distribution reconstruction 2. Adaptive Vth tracking 3. LDPC codes with soft-decoding (help correct more bit errors). Flash Memory Summit 2 4

5 The Methods to Overcome Retention and Endurance Disturbance EV PV PV2 PV3 PV4 PV5 PV6 PV7 Vth Vth MSB CSB MSB LSB MSB CSB MSB Vth MSB CSB MSB LSB MSB CSB MSB Flash Memory Summit 2 5

6 Detecting LSB Direction and Shift Amount B A C Target State State State 2 State 3 State 4 State 5 State 6 State 7 Binary Binary A B C Flash Memory Summit 2 6

7 Detecting CSB Direction and Shift Amount Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary Binary è è è è Flash Memory Summit 2 7

8 Detecting MSB Direction and Shift Amount Binary Binary Binary Binary Binary Binary Binary Binary Binary The MSB Vth is equal to two CSB cases. The shift probability of the upper two Vth is greater than the lower two. When the lower two Vth values are fixed, shift the upper two Vth first and fine-tune them to the best location. If the upper two Vth values stay at the best location but are still uncorrectable, fix these values to the best location and shift the lower two Vth. Flash Memory Summit 2 8

9 Tracking Vth in One Block The data in the same block suffers similar disturbances. Only the first page applies the detailed Vth tracking. All the pages other than the first page follow the previous page s Vth location, and the location for the next page is going to be fine-tuned. After Vth tracking, the pure noise effect shall be taken into account. Flash Memory Summit 2 9

10 Soft-Decoding for Larger Noise Flash Memory Summit 2

11 Performance of LDPC Soft-Decoding over AWGN 5th 2nd st 3rd 4th UBER = codewrod error rate message bit codewrod error = 892 bit rate Flash Memory Summit 2

12 LDPC Real Endurance Test LDPC hard-decoding can correct most of errors since the flash storage system behaves like BCH. Unit-amount Err-bit BCH is unworkable, but LDPC soft-decoding is workable. The test shows LDPC provides a highly reliable system. Flash Memory Summit 2 2

13 Impact of Soft-Decoding Soft-decoding improves the data storage reliability. Acquiring soft information will consume more power on read. The higher transfer throughput of flash interface is required. The KB-based LDPC decoder for USB/SD2. applications is around four times as complex as the BCH decoder with the same constraints (code rate, message length, etc.) The overall gate counts of USB/SD2. controllers turn into double when the BCH is replaced by LDPC. Flash Memory Summit 2 3

14 Additional Benefits of Flash Controllers with LDPC The testing cost increases as the NAND flash process continues to advance (3x 2x 2y x nm). The testing cost of high-capacity flash chip (8/6 GB above) may be close to, or exceed the controller s price. Examples: A: Flash controller with BCH + flash-die cost Lower yield + higher testing cost B: Flash controller with LDPC + flash-die cost Higher yield + lower testing cost Example B may be a better cost-efficient solution. Flash Memory Summit 2 4

15 Examples of Different Endurance Performance in 4GB TLC Flash 4GB x 4K = 6TB EV PV PV2 PV3 PV4 PV5 PV6 PV7 2.6GB x 2K = 53TB EV PV PV2 PV3 Vt Vth h LSB is all FF.3GB x 2K = 6TB EV PV Vt Vth h LSB is all FF CSB is all FF Vt Vth h Flash Memory Summit 2 5

16 Endurance Enhancement of TLC Flash In some applications, only the wear capacity (not the data capacity) needs to be considered: TLC access period: 4GB x 4K (cycle) = 6TB MLC access period: 2.6GB x 6K (cycle) = 4.6TB SLC access period:.3gb x 8K (cycle) = 4TB Total media-wear capacity = 6TB X improvement Flash Memory Summit 2 6

17 Conclusion Vth tracking and LDPC soft-decoding provide a good error correction capability to reduce the endurance and retention disturbance. With the endurance enhancement, TLC flash can fit in a variety of embedded applications. Silicon Motion s NAND flash controllers equipped with robust LDPC decoding engine offer one of the best cost-efficient systems and are ready for tests and validations. Flash Memory Summit 2 7

18 Thank You! Q & A Flash Memory Summit 2 8