A Self Learning Algorithm for NAND Flash Controllers

Transcription

1 A Self Learning Algorithm for NAND Flash Controllers Hao Zhi, Lee Firmware Manager Core Storage Electronics Corp./Phison Electronics Corp. Santa Clara, CA 1

2 Outline Basic FW Architecture Challenges & Problems Self-learning & Adaptive Algorithm Conclusion Santa Clara, CA 2

3 Basic FW Architecture Santa Clara, CA 3

4 Brief Overview Command Task Management Buffer Management Logical-To-Physical Mapping Garbage Collection Wear Leveling Management Read Disturb Management Flash Operation Management Buffer Management Flash Error Recovery Bad Block Management Host Interface Layer (HIL) Flash Translation Layer (FTL) Flash Interface Layer (FIL) Santa Clara, CA 4

5 Challenges & Problems Santa Clara, CA 5

6 Performance Read/Write Latency Different hosts have different I/O patterns Inefficient host latency management results in unstable performance Idle Time Operations Controller performs background operations or enters power saving mode during system idle Redundant operations will not only consume more power, but also impact WAF and latency time of next command Santa Clara, CA 6

7 Endurance Data Integrity Sudden power loss, data retention and read disturbance will lead to data corruption in NAND flash Device Lifetime NAND flash has limited P/E cycle Unbalance SLC/TLC block usage will induce higher WAF and cause NAND flash to wear out quickly Santa Clara, CA 7

8 Cost Over Provision WAF can be greatly reduced by allocating more spare blocks However, higher OP means lesser logical space for user Santa Clara, CA 8

9 Flexibility Firmware Update Different host platforms have dissimilar IO patterns Several FW versions optimized to serve each platform can be costly to maintain Santa Clara, CA 9

10 Self Learning & Adaptive Algorithm Santa Clara, CA 10

11 Objective FW with configurable parameters is simply not enough The following to be considered a. Data/pattern aware b. Self adaptive c. Self learning Santa Clara, CA 11

12 Key Parameters HOST 1. Read/Write IO Pattern 2. System Idle Behavior HOST FTL 1. Block Usage 2. Block Density 3. Block Age 4. Table Hit Pattern Feed parameters & pattern FW Algorithm Generate adaptive strategies FTL NAND FLASH 1. Erase Count 2. Read Count 3. Flash Error Condition NAND Flash Santa Clara, CA 12

13 Dynamic Read Recovery Strategy Due to the reliability issues of 3D NAND, the read recovery flow has been more sophisticated and time consuming than before Such as, the expansion of read retry tables in NAND flash The device performance can be severely impacted especially during end of life Santa Clara, CA 13

14 Dynamic Read Recovery Strategy Read fail Feedback to improve read recovery strategy based on successful recovery Decision for read recovery strategy Read recovery flow Controller can monitor the status of NAND flash and learn from previous recovery statistics to optimize the recovery flow Santa Clara, CA 14

15 Dynamic Read Recovery Strategy Adaptive recovery strategy can rearrange the priority of recovery flow Recipe 1 Recipe 2 Recipe M Recipe N Higher chance of immediate recovery Controller will eventually learn along the iterative process and determine the best approach Santa Clara, CA 15

16 Idle Time Optimization Controller usually waits for a period of idle time (preconfigured by user) and then performs background operations or enters power saving mode During these operations, some data will be programmed into NAND flash Santa Clara, CA 16

17 Idle Time Optimization Host idle time Previous host command Next host command Idle wait time pre-configured Enter power saving mode or perform background operations Program to NAND flash (i.e., flush cache data, save table, etc.) Santa Clara, CA 17

18 Idle Time Optimization Most of the idle time is lower than 10ms Main contribution of the idle time is more than 100ms However, different hosts may have different idle time behavior Santa Clara, CA 18

19 Idle Time Optimization Host idle time Previous host command Next host command Idle wait time pre-configured Enter power saving mode or perform background operations Program to NAND flash (i.e., flush cache data, save table, etc.) Redundant NAND flash program operations will increase erase count Santa Clara, CA 19

20 Idle Time Optimization What if the controller can learn from the host behavior and predict for an optimized strategy? Idle time prediction Controller learns from the idle time detected and provides feedback to improve prediction Decision for idle time strategy Idle time detection (when next host CMD arrives) If predicted time is short, wait for a time period If next host command is still not coming, proceed to power saving mode or background operation Santa Clara, CA 20

21 Idle Time Optimization Host idle time Previous host command Next host command Idle wait time pre-configured Wait for a time period An adaptive idle time strategy can greatly reduce redundant programs to NAND flash Santa Clara, CA 21

22 SLC Erase Count per day Idle Time Optimization Simulation Results About 45% improvement Before Simulation results based on host usage model Saved 45% of NAND flash program during idle time After Santa Clara, CA 22

23 Mixed Pool Dynamic Wear Leveling Only for SLC use Only for TLC use SLC Pool TLC Pool The number of SLC/TLC blocks are usually allocated during device initialization We expect both SLC/TLC pools to wear out equally during device end of life Santa Clara, CA 23

24 Erase Count Mixed Pool Dynamic Wear Leveling Increment of erase count SLC Max Erase Count: 40K TLC Max Erase Count: 1.5K SLC max erase count SLC Device will fail early when either one of the pool has achieved its max erase count TLC max erase count TLC Time However, different host I/O behavior might have different impact on SLC/TLC block usage Santa Clara, CA 24

25 Mixed Pool Dynamic Wear Leveling Only for SLC use Only for TLC use Share TLC pool when SLC pool is over consumed SLC Pool TLC Pool Controller can constantly monitor the erase count ratio of both pools and dynamically configure the block selection algorithm to keep within reasonable TLC/SLC ratio Santa Clara, CA 25

26 Erase Count Mixed Pool Dynamic Wear Leveling Increment of erase count SLC Max Erase Count: 40K TLC Max Erase Count: 1.5K SLC max erase count TLC max erase count SLC SLC" TLC TLC" Lifetime extended by 10% Time Simulation results based on host usage model This will prevent device to fail early due to wear out Santa Clara, CA 26

27 Conclusion By exploring the key parameters of host behavior, system data structures, and NAND flash condition, a self learning FTL with simple adaptive design can benefit storage device in terms of performance, endurance, cost and flexibility Santa Clara, CA 27

28 THANK YOU Santa Clara, CA 28