A Buffer Replacement Algorithm Exploiting Multi-Chip Parallelism in Solid State Disks

Transcription

1 A Buffer Replacement Algorithm Exploiting Multi-Chip Parallelism in Solid State Disks Jinho Seol, Hyotaek Shim, Jaegeuk Kim, and Seungryoul Maeng Division of Computer Science School of Electrical Engineering and Computer Science Korea Advanced Institute of Science and Technology (KAIST) CASES 09, Grenoble, France, October 11-16, 2009.

2 Outline Introduction Background Related Work Proposed Scheme Evaluation Conclusion

3 Introduction (1/3) Advantages of NAND flash memory low power consumption, small size, and lightweight Solid State Disks (SSDs) achieve short start-up time, fast random accesses, and low power consumption eliminating the mechanical overheads of magnetic disks

4 Introduction (2/3) To enhance the overall performance and capacity, SSDs employ multi-chip architecture multiple operations are distributed over flash chips Problem: the unit of NAND flash memory has become larger than the unit of a host interface as the density of NAND flash memory increases because of the difference of the units, SSD sometimes should write a partially-filled page, which turn into a readmodify-write operation

5 Goal Introduction (3/3) to alleviate the overhead of read-modify-write operations while exploiting a multi-chip parallelism analyze the overhead of read-modify-write operations in a multi-chip architecture propose a buffer replacement algorithm called MCA (Multi-Chip based replacement Algorithm)

6 Background (1/5) NAND flash memory characteristics three main operations: read, write, and erase erase-before-write: if a page is once written, it cannot be overwritten until the block that the page belongs to is erased two types of NAND flash memories: Single-Level Cell (SLC) & Multi-Level Cell (MLC) MLC is widely used in general storage systems because of it s better capacity per price

7 Overall architecture of SSD Background (2/5) two main functions of Flash Translation Layer (FTL) Address translation from a logical sector address to a physical memory address Garbage collection that moves valid pages to another block and erases blocks to reclaim invalid pages

8 buffer cache Background (3/5) concerns only write requests most read requests are processed by the buffer cache in a host system effectively reduce the number of write requests to NAND flash memory absorbing a number of requests by replacing the data in it sends write requests to FTL when it is full or a flush request is received when FTL receives the write requests, FTL writes the data to NAND flash memory

9 Background (4/5) Multi-chip based storage system for large-capacity and high-performance two types of multi-chip configurations depending on whether a data bus is shared or not shared control architecture all flash chips have their own data path better performance but need higher cost of implementation shared bus architecture the data bus is shared among a number of flash chips Problem» when a chip on a shared bus want to send/receive data, it has to wait until the bus is idle» Sol: multi-channel architecture

10 Background (5/5) multi-channel architecture bus congestion is distributed over all channels significantly alleviate performance degradation

11 Related Work (1/4) two categories of buffer cache algorithms hit ratio based algorithm concentrate on increasing cache hit ratio such as LRU FTL based algorithm reduce the overhead of garbage collection by exploiting the characteristics of FTLs such as FAB, BPLRU not feasible for a high-performance storage system long latencies on a specific chip to write all pages in a block at once

12 Related Work (2/4) Kang et al. proposed three optimization techniques to exploit the parallelism striping technique splits a request into sub-requests over multiple channels interleaving technique a number of requests are handled simultaneously across several channels pipelining technique best choice of single channel architecture two requests are not handled simultaneously the second request can be transferred after transferring the first request while the first request is being written

13 Related Work (3/4) Chang et al. have approached in terms of an assignment policy to exploit the parallelism when FTL receives read request the FTL knows the chip to read because the requested page is stored in a specific chip already write request assigning a chip is required to write a page How to select a chip? static chip assignment policy simply using a modulo operation does not guarantee that all chips are used evenly dynamic chip assignment policy a chip that is idle and has the largest number of free pages is selected

14 Related Work (4/4) the chip-level parallelism is achieved by using dynamic chip assignment policy. Thus, the pipelining technique is achieved naturally.

15 Proposed Scheme (1/6) basic operation unit of secondary storage systems is a sector of 512 bytes basic operation unit of flash memory is a page of 2048 or 4096 bytes according to the manufacturer because of the difference in size, SSDs need following steps to write a single sector reading the page where a requested sector is stored modifying the page with the requested sector writing the modified page called a read-modify-write operation 4K page 512K sector 4K page 512K sector 4K page

16 Proposed Scheme (2/6) Two reasons for triggering a read-modify-write operation a small request size a request is smaller than a page often when write requests are random alignment problem of a host system request does not align with a page appears frequently in ordinary file systems such as NTFS and ext3

17 Proposed Scheme (3/6) because a read-modify-write operation consists of serial operations, it causes a chip-waiting problem Time A: flush Page 2 Page2 is a partial page, need to read the pre-existing page the pre-existing page is in Chip2, but Chip2 is busy, so write operation is delayed Time B: Chip2 is now idle

18 Proposed Scheme (4/6) Multi-Chip based replacement algorithm (MCA) reschedule the flushing order by considering the state of NAND flash chips, which denote busy or idle target chip: a candidate chip to perform a write operation which is idle and has the largest number of free pages is selected victim page: a candidate page to be evicted from the buffer cache by LRU order if the victim page is full page: write the page to the target chip partial page: is flushed as long as the chip where the pre-existing page of the flushed page exists is idle

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20 the operation of Page0 is delayed until Chip2 become idle chip-waiting problem occurs and also disrupts pipelining

21 Evaluation (1/9) Simulation environment implement a trace-driven SSD simulator using SystemC

22 Evaluation (2/9) time overheads for software processing is not considered measure bus and chip latencies that occupy the major portion of the total cost as the page transfer time is 105.6μs and the write operation time is 800μs 8 flash chips are used on a channel bus to hide write operation delay several physical pages are grouped into one logical page called a super page to enhance the parallelism with a multi-channel architecture

23 Evaluation (3/9) implement a large super page size by extending channels use 2 channels to use 8 KB super page as Fig. 13, one super page is stripped into 2 channels ex: a 8KB super page, whose logical page number is 3, consists of the first page of Chip1 and the first page of Chip5.

24 Workload NTFS: DiskMon ext3: blktrace HFS+: fs_usage Evaluation (4/9)

25 22% but consume up to 59% of total write time dynamic chip assignment policy page-level LRU replacement algorithm same experiment with 16MB write buffer cache 21% partial pages consume 58% write time in WINXP enlarging buffer size is not an effective way to reduce the overhead of read-modify-write operations

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27 Fig. 10(a) the main difference is Chip Wait Time DA-MCA focuses on reducing chip wait time, so this difference is linked directly with performance improvement. Fig. 10(b) the main difference is Write Time the total execution time is reduced as much as the time that is reduced during writing

28 Evaluation (8/9) MCA does not have a particular effect on hit ratio of the pure LRU scheme.

29 Evaluation (9/9) Generally, a large super page size shows better performance When super page is 4KB: 20% performance improvement is achieved by using MCA 16KB: over 30% performance improvement

30 Conclusion The read-modify-write operations disrupt pipelining, they are major obstacles to exploiting parallelism. The proposed algorithm, Multi-Chip based replacement algorithm (MCA), can improve performance through enhanced parallelism by rescheduling the order of write operations.