ASIC/Merchant Silicon Chip-Based Flash Controllers

Transcription

1 ASIC/erchant Silicon Chip-Based Flash Controllers Jeff Yang Silicon otion Flash emory Summit 27 Santa Clara, CA

2 Basic architecture TC region SC region Write channel Read channel Buffer for DATA CP Buffer for others Host-Interface DRA Flash emory Summit 27 Santa Clara, CA 2

3 Write channel Application combinations on TC/QC TC region SC region Read channel. SC caching. Data always write into SC. A Fixed portion of SC regard as a cache buffer. Performance boost on SC caching. Background GC to TC block. 2. TC direct. Only a very small portion for system usage and small random write data. A stable sustained write performance. 3. Dynamic SC. ess than /3 capacity threshold, using SC. aximizing performance boosting period. Background GC to TC block. Buffer for DATA Host-Interface CP DRA Buffer for others. Full size DRA For host data write caching. Full lookup table. 2. Non-DRA Extremely low cost. Optimize for user experience. ore system info access from SC blocks. 3. Small DRA. Full lookup table on external buffer No host data buffer. Flash emory Summit 26 Santa Clara, CA 3

4 Write channel Different TC reliability issue TC region SC region Read channel. 3D. One-pass program, two-pass program, multi-pass program. 2. Program failure protection flow. Program failure range. Read back data from flash cache buffer. DRA back up. SC back up, SRA backup. 3. One W open and ulti-w short. Need raid or read back check after program. 4. TC/SC dynamic changing usage. TC endurance calculation issue. 5. Internal copy back for SC to TC Internal read without ECC correction Buffer for DATA CP Buffer for others Host-Interface DRA Flash emory Summit 27 Santa Clara, CA 4

5 3D Challenge: Support all combinations and cost efficiency External SC usage buffer One-pass SC caching Full DRA Two-pass ulti-pass TC direct SC/TC dynamic Non-DRA Partial DRA Flash emory Summit 27 Copyright Silicon otion, Inc., 22. All Rights Reserved. 5

6 SI Product comparison Full DRA Partial DRA None DRA (HB) None DRA Full Capacity Seq Perf 5 25 Random Perf DRA High Perf GC efficiency ow W/A ow complexity Partial DRA GC efficiency Capacity limited by 2P address bit (8TB) None DRA Perf still good for CD None DRA (HB) Random perf W/A GC efficiency Cost FW complexity Capacity limitation (2TB) DRA bandwidth limitation Power consumption ed Random Perf (DRA 2P buffer) ed W/A High W/A ow Random Perf (SRA 2P buffer) Program Failure High capacity support Same as None DRA ore complex than None DRA

7 SI Product comparison Full DRA Partial DRA None DRA (HB) None DRA Full Capacity Seq Perf 5 25 Random Perf DRA High Perf GC efficiency ow W/A ow complexity Partial DRA GC efficiency Capacity limited by 2P address bit (8TB) None DRA Perf still good for CD None DRA (HB) Random perf W/A GC efficiency Cost FW complexity Capacity limitation (2TB) DRA bandwidth limitation Power consumption ed Random Perf (DRA 2P buffer) ed W/A High W/A ow Random Perf (SRA 2P buffer) Program Failure High capacity support Same as None DRA ore complex than None DRA

8 SI Product comparison Full DRA Partial DRA None DRA (HB) None DRA Full Capacity Seq Perf 5 25 Random Perf DRA High Perf GC efficiency ow W/A ow complexity Partial DRA GC efficiency Capacity limited by 2P address bit (8TB) None DRA Perf still good for CD None DRA (HB) Random perf W/A GC efficiency Cost FW complexity Capacity limitation (2TB) DRA bandwidth limitation Power consumption ed Random Perf (DRA 2P buffer) ed W/A High W/A ow Random Perf (SRA 2P buffer) Program Failure High capacity support Same as None DRA ore complex than None DRA

9 SI Product comparison Full DRA Partial DRA None DRA (HB) None DRA Full Capacity Seq Perf 5 25 Random Perf DRA High Perf GC efficiency ow W/A ow complexity Partial DRA GC efficiency Capacity limited by 2P address bit (8TB) None DRA Perf still good for CD None DRA (HB) Random perf W/A GC efficiency Cost FW complexity Capacity limitation (2TB) DRA bandwidth limitation Power consumption ed Random Perf (DRA 2P buffer) ed W/A High W/A ow Random Perf (SRA 2P buffer) Program Failure High capacity support Same as None DRA ore complex than None DRA

10 Traditional Error recovery flow Flash emory Summit 23 Santa Clara, CA Flash emory Summit 27 Santa Clara, CA

11 Soft-information interface SEQ DSP SEQ DSP SEQ7 DSP7 2nd read Normal read 3rd read Write channel x= x= Decoder y=7 y=6 y=5 y=4 y=3 y=2 y= y= RAW data Vth Buffer for DATA CP Sub-system Buffer for others Encode Host-Interface DRA In order to provide better decoder s correction capability, using the soft-info to get more reliability bits. NAND interface support. Traditional read/retry interface. Direct soft-info interface. SI Confidential

12 DSP engine s buffer size Buffer for Sign R apping Buffer 2 for Soft-bit Buffer 2 for Soft-bit Compression The buffer size is the capability to contain the number of chunks soft-bit. Access addition soft-info from NAND may need additional read busy time. Read the soft-bit under the same busy time will have higher efficiency, but buffer size requirement is huge. 2

13 Soft-decoding throughput limitation One Transfer time = 2.5ns/B x 8432B = 46us (4Ts) Assume DSP-buffer size 6KB. 9 tr time + 2 transfer-time = 9x(us) + 2 x (46us) = 452us Throughput = 64KB/452us = 44B/sec Assume DSP-buffer size 64KB. 3tR time + 2 transfer-time = 3x(us) + 8 x(46us) = 668us. Throughput = 64KB/668us = 95B/sec In Client SSD applications, Soft-decoding will regard as the ERROR-Recovery flow. We will not ask the throughput under recovery mode. But we will take care the recovery mode trigger rate. 3

14 Block 2D BOCK W W W 2 W 3 W 4 W 5 W Failure range from 2D to 3D. Program order Damage range of Program fail Damage range of Word-line open Damage range of two Word-line short Block 3D BOCK W W N N Damage range of Program fail / Wordline Open Damage range of Word-line short W W Program order 4

15 3D NAND Challenges Each 3D generation will increase the layer number by 3~5%. High-aspect ratio channel hole etch. Cell current reduction is seriously concerned. Reduce the read-voltage to improve the read-count (degradation the read-disturbance) make cell current worse. Different cell characteristics for each W. (program-speed, cell-tocell interference, retention) Poor retention characteristics. Not easy to screen out some defects. Especially on bit-column related defect. Flash emory Summit 27 Santa Clara, CA Ref: Evolution of NAND flash memory: from 2D to 3D 27 IW 5

16 DSP algorithm for the Vth-tracking + read Harddecoding Correctable? Yes No +3 read Soft-decoding -sign, -soft Correctable? Yes No Get a correctable code word. Gather the tracking result st 2 nd 3 rd Soft-decoding +5 read -sign, 2-soft Correctable? Yes No Smart prediction the right center sensing point st 2 nd 3 rd 4 th 5 th Soft-decoding +7 read -sign, 2-soft Correctable? Yes No No Over-hill detection will prevent the Vth-tracking into wrong direction. st 6 th 2 nd 3 rd 7 th 4 th 5 th Keep in +7 read Adjust the decoding parameter ncorrectable && ~max-loop Yes Read fail (go to next error recovery stage) The parameter include:. Sensing step size. 2. Decoder internal coef. 3. Dynamic tuning the R 4. 6

17 ECC design loop related to NAND characteristics. We already have 7 th generation DPC decoder. Keep improving the DPC performance. For higher throughput ~8GB/sec, we may go back to step. After 28nm process, the design iteration depth will from code-construction to trial APR. EX: Find the Routing congestion issue in step 4, it may need to solve from step. NAND error behavior. Soft/hard. NAND Page size and reserved spare area. ECC chunk size Data transfer efficiency(data-path overhead) APR utilization from different process node. Firmware enabling error recovery Code truction SOC integration and Firmware control flow Encoding and decoding algorithm Hardware architecture performance trade-off Encoder scheme. Configurable and power consumption. Decoder algorithm prove and evaluate with NAND model. FPGA emulation for DPC decoding algorithm. Throughput requirement trade-off. Power consumption trade-off. Correction capability trade-off. Complexity trade-off. 7

18 Before the RAID protect flow.. DRA/ DRA-less/ Small DRA Capacity (RAID overhead) Binary/arbitrary SC-first/ TC-direct write/ Dynamic SC Program failure DRA-backup/ Flash-cache/ RAID recover/ One-pass / ulti-pass/ Pair-page mapping All the issues combine together! W open Failure range W to W short Failure range Recovery latency BT THE SAE CONCEPT IS.

19 Don t put eggs in the same basket. Block 3D BOCK W W N Damage range of Program fail / Wordline Open Damage range of Word-line short Put the pages in the same failure range into different RAID-Group RAID-Group SB CSB RAID-Group 2 SB CSB RAID-Group X SB CSB N SB SB SB W Program order Different flash will have different failure range. Different application will have different RAID encoding flow. Reserve the maximum flexibility for all controller to support all kinds of 2D/3D NAND. If you don t want to use RAID, What alternative you still have? Read-back check after program. 9

20 atlat demo platform. atlab interfa ce CD translati on SATA/P CIE controll er atlab base program. Gather the data and process by matlab. ore easily to show the figure. Provide high level controller interface. NAND access CD packet Hookup the atlab API to SB/PCIE driver. Provide several different NAND access functions to provide atlab high level control interface. SI controller specification function demo. (Adaptive chargine/vth-trakcing/dpc soft-decoding). Provide a function call. Firmware implement the Vendor CD to serve all kinds of NAND access. Complex function implement by ARC/AR firmware to provide specific function demo. 2

21 ECC tool update with all NAND. SATA 2258/2259 PCIE 226/2262/2263/227/2264 Color Vth-distribution. All W Vth-distribution. Error recovery golden flow. Soft-info fetch correctness analysis. Automation RTBB analysis. (OE special request support) ECC decoding/encoding, randomizer model. ISPP tuning for verification. 2

22 Thanks. Q&A 22