An LDPC-Enabled Flash Controller in 40 nm CMOS

Transcription

1 An LDPC-Enabled Flash Controller in 40 nm CMOS Marvell Semiconductor Engling Yeo Santa Clara, CA 1

2 Outline Error correction requirements LDPC Codes ECC architecture SOC integration Conclusion Santa Clara, CA 2

3 Outline Error correction requirements LDPC Codes ECC architecture SOC integration Conclusion Santa Clara, CA 3

4 Diminishing P/E Ratings P/E Rating VDD SLC MLC TLC Santa Clara, CA 4 GND

5 ECC Affects Many Parameters 0 Aging device -1 ECC Failure Rate Raw BER of device progressively decreases as a result of : Reduced device sizes Reduced power supplies Reduced R/W access time Aging device Performance of BCH(t=76) decoder Achieves SFR < RBER= SFR Reduced power supplies Reduced device size -3-4 Reduced R/W access time -5-3 Santa Clara, CA -2 Raw BER -1 5

6 P/E Cycle Expectancy As Function of Sector Failure Rate Tolerable Sector Failure Rate 0 TLC MLC -6 Advanced ECC -12 Improvement in P/E Expectancy P/E Cycles Santa Clara, CA 6

7 Outline Error correction requirements LDPC Codes ECC architecture SOC integration Conclusion Santa Clara, CA 7

8 LDPC Decoding: Belief Propagation Each event occurs with some prior probability. Posterior probability based on inference from a number of related events. WHO IS Game Plan CHAMPION Weather Players Age Players Salaries Injured Players Game Location Game Date 8 Santa Clara, CA 8

9 Constrained Coding and LDPC Decoding Each set represents a group of constrained bits e.g. even parity, cyclic codewords Decoding based on inferences passed between adjacent neighbors H B D G C A E F Santa Clara, CA 9

10 Low Density Parity Codes Advantages: Best class of codes to approach theoretical limits of error correction strengths. Well-studied theoretical approaches in the last decade. Has been deployed in magnetic storage since Choice error correction codes e.g. IEEE N, AC, ITU G.hn, GBase-T, DVB-S2, etc. Disadvantages: Difficult and intractable VLSI implementations. Higher power dissipation than traditional BCH solutions. Santa Clara, CA

11 Why LDPC? More stringent demands for error correction capabilities tips the favor towards LDPC decoder. LDPC Decoders can provide flexibility in: Throughput. Exploit inherent parallel nature of LDPC decoding Complexity. Tradeoff decoding complexity against error correction strength. Santa Clara, CA 11

12 Relative Complexities Santa Clara, CA 12

13 Decoder Complexity Comparison VLSI Gate Count 7 6 LDPC 5 Correction strength LDPC decoders have a higher initial barrier, but complexity does not increase as quickly as BCH decoders at higher correction strengths. Santa Clara, CA 13

14 Outline Error correction requirements LDPC Codes ECC architecture SOC integration Conclusion Santa Clara, CA 14

15 Reliability-Aware ECC Architecture (RAECC) Exploits unique characteristic of Solid State Memory: Data reliability degrades as device ages. At the beginning of life, reliability is typically very good. However, towards the end of life, the number of blocks that require extensive ECC operation to recover the data becomes higher. Santa Clara, CA 15

16 Reliability-Aware LDPC Architecture Two modes of LDPC decoding with BCH Decoding. 1. Low Power mode (LP-LDPC) can be used with high reliability data (RBER < -3 ). 2. Strong Correction mode (SC-LDPC) provides more error correction, with increased power consumption 3. A low-correction BCH decoder provides guard against weaker performance of LP- LDPC decoder. Santa Clara, CA 16

17 Reliability-Aware ECC Architecture (RAECC) Pros: low power low complexity, Cons: Possible performance degradation at the end of life. Santa Clara, CA 17

18 LDPC Performance against BCH t= UBER LP Mode LDPC rate 0.9 SC Mode LDPC rate 0.9 BCH: t= RBER -1 LDPC-based ECC outperforms existing BCH code Santa Clara, CA 18

19 Outline Error correction requirements ECC architecture LDPC Codes SOC integration Conclusion Santa Clara, CA 19

20 Coeus Flash Controller SOC 40 nm CMOS process Enhanced Reliability-Aware LDPC ECC engine Support for two channels of NAND flash devices with 4 Chip Enable (CE) per channel Support for ONFI 1, ONFI 2.0, ONFI 2.2, ONFI 2.3, and Toggle mode Support for MMC and embedded MMC (emmc) host interfaces Embedded ARM CPU core ARM V6T2 architecture with Thumb-2 support Santa Clara, CA 20

21 Coeus Architecture Ch0 2 Channels 4 CEs/ Ch ON NFI Interf face Flash Controller DMA Master LDPC CPU ROM Power Management XBar LPDDR1/2 Controller SDMMC Controller SD or MMC 1, 4, or 8-bit Data Interface Ch1 Sequencer I/O SPI RAM UART GPIO Santa Clara, CA 21

22 LDPC consumes less power than BCH at the same correction strength < 50mW LDPC Read Power BCH Aux LDPC LP-LDPC Santa Clara, CA 22

23 Coeus NAND Flash Controller SOC CPU LDPC ECC Engine ONFI Interface Santa Clara, CA 23

24 Outline Error correction requirements LDPC Codes ECC architecture SOC integration Conclusion Santa Clara, CA 24

25 Conclusion Reliability-aware LDPC architecture combines a low-power mode with a strong correction mode to provide optimal correction-power tradeoff at various stage of NAND life cycle. Lower power dissipation than traditional BCH ECC. See you at Marvell Semiconductor Booth Santa Clara, CA 25