DEMO MANUAL DC981A/DC981B LTC4263 Main Board, Single Port Autonomous PSE/Daughter Card PSE. Description. Performance Summary. Quick Start Procedure

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1 Description Demonstration circuits 98A and 98B feature the LTC in single port Power over Ethernet (PoE) power sourcing equipment (PSE) midspan and endpoint solutions. The LTC is an autonomous single-channel PSE controller for use in IEEE80.af compliant PoE systems. It includes an onboard planar power MOSFET, internal inrush, current limit, and short-circuit control, powered device (PD) detection and classification circuitry, and selectable AC or DC disconnect sensing. Onboard control algorithms provide complete PSE control operation without the need of a microcontroller. The LTC simplifies PSE DEMO MANUAL LTC Main Board, Single Port Autonomous PSE/Daughter Card PSE implementation, needing only a single 8V supply and a small number of passive support components. Other options shown on the DC98A include legacy PD detection enable, midspan backoff timer enable, power class enforce mode, and power management enable. An LED for each port is driven by the respective LTC to indicate the state of the port. Design files for this circuit board are available at L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Performance Summary Table. Typical DC98, Specifications are at T A = C PARAMETER CONDITION VALUE Supply Voltage Voltage for IEEE80.af Compliance at Port Output V to 7V Midspan Mode Detection Backoff Midspan Enabled, Failed Detection.s Detection Range Valid IEEE80.af PD Detection 7kΩ to 9.7kΩ Set Maximum Allocated Power Power Management Enabled, RPM =.kω 7W Ethernet Powered Pairs Pinout Endpoint PSE, Alternative A (MDI) Midspan PSE, Alternative B /(+), /( ) /(+), 7/8 ( ) Quick Start Procedure Demonstration circuits 98A and 98B are easy to set up to evaluate the performance of the LTC. Refer to Figure for proper measurement equipment setup and follow the procedure below.. Place jumpers in the following positions: JP EN JP EN JP DIS JP AC JP AC JP EN. Insert daughter card (DC98B) to main board (DC98A) at polarized connector J.. Apply 8V across and VSS.. Connect a scope probe at VOUT_MD and VOUT_EP both referenced to positive rail.. Connect a valid PD to either midspan PSE or endpoint PSE.. Connect a second PD to the open port.

2 Operating Principles Figure. Basic Equipment Setup

3 Operating Principles The DC98 provides two implementations of a PSE controlled by the LTC, a midspan PSE and an endpoint PSE. A single 8V supply is all that is required to power the board. This in turn provides power to the midspan PSE and endpoint PSE outputs. On each solution, an LTC provides detection, classification, power management, safe power on, port current limit, and disconnect detection. Midspan PSE In the midspan solution, a legacy device (router, switch, etc.) that does not have PoE is connected to MIDSPAN IN. Data is passed through to MIDSPAN OUT along with PoE which goes out to a PD. Power is applied directly to Ethernet pairs / and 7/8. The LTC circuitry is located in a small layout area behind the RJ connector and switches power on the negative rail. To show the different functions of the LTC, jumpers allow for the user to select the options of AC or DC disconnect, legacy detection, midspan backoff timing, and class enforcement. An LED that shows the status of the port is driven by a switcher in the LTC to improve efficiency when VDD is provided internally. Push button switch SW ties the shutdown pin to ground to disable the LTC in the midspan solution. A PSE implementing alternative B pin out must back off from detection for at least two seconds after a failed attempt. This is to avoid conflict of detection, for example, should a potential endpoint PSE and midspan PSE be connected to the same PD. To enable this feature, set JP to DIS. JP ties the MIDSPAN pin to VDD to enable the LTC backoff timer or to VSS to disable. A.s delay occurs after every failed detect cycle unless the result is open circuit. If held at VSS, no delay occurs after failed detect cycles. Endpoint PSE The endpoint solution is primarily shown on a small daughter card (DC98B). This card is the same height and width as the integrated RJ connector that it slides behind on the main board (DC98A). The RJ includes Ethernet magnetics and common mode termination. A layout option shows the same components can be placed under the same RJ connector. The minimum connections to the daughter card are VSS, and VOUT. Power is switched over from the daughter card out to the Ethernet data pairs (/ and /). A PHY can be connected to the TO PHY connector to pass data through to the data pairs along with PoE. LED drive and power management pins are also brought out for additional board functions. The board is set up for AC disconnect, but can be reworked for DC disconnect by removing components and replacing with shorts in certain locations. Two solder jumpers also provide selectable options for legacy detection and class enforce. Power Management The midspan and endpoint PSEs, although separate solutions on the DC98, are tied together at the PWRMGT pin for demonstration of the LTC power management capability. Programmable onboard power management circuitry allows multiple LTCs to allocate and share power in multiport systems, allowing maximum utilization of the 8V power supply all without the intervention of a host processor. The LTC sources current (IPM) at the PWRMGT pin proportional to the class of the PD that it is powering. The voltage of this pin (VPM) is checked before powering the port (Table ). The port will not turn on if this pin is more than V above VSS. The PWRMGT pins of the LTCs are tied together and connect to a resistor (RPM) and capacitor (CPM) in parallel to VSS to implement power management. This resistor is selected with the following equation: R PM = kω W/P FULL_LOAD On the DC98A, the default RPM is.kω for a full load power of 7W. Table. Power Management Voltage PD CLASS POWER IPM (TYP) VPM* REQUEST Class W 9μA mv Class 7W μa 09mV Class 0,, or.w 7μA 90mV *RPM =.kω

4 Operating Principles Table. Powered Device Combinations PD COMBINATION ST PD ND PD Class / Class Powered Powered Class / Class Powered Powered Class / Class ** Powered Power Denied Class / Class Powered Powered Class / Class ** Powered Power Denied Class **/ Class ** Powered Power Denied **Class substitutable with Class 0 or. If power management is not used, move JP to DIS to tie the PWRMGT pins to VSS and disable this feature. Class Enforce Mode ENFORCE CLASS jumper JP ties the ENFCLS pin of the LTC to either VDD or VSS to respectively enable or disable class enforce current limits. If held at VDD, the LTC will reduce the ICUT threshold for Class or Class PDs. If ENFCLS is held at VSS, ICUT remains at 7mA (typical) for all classes. Table. Port Current Limit According to Class PD CLASS CURRENT THRESHOLD (TYPICAL) Class 00mA Class 7mA Class 0,,, or Class 7mA Enforce Disabled LED Drive An LED pin indicates the state of the port controlled by the LTC. When the port is powered, the LED is on; when disconnected or detecting, the LED is off. If an invalid signature is detected or a fault occurs, the LED will flash a pattern that the user or host system can read to indicate the nature of the problem. When run from a single 8V supply, the LED pin can operate as a simple switching current source to reduce power dissipation in the LED drive circuitry. VDD Option The logic V power supply can be supplied from the internal LTC V supply or an external V supply when above the internal supply. If the internal regulator is used, this pin should only be connected to the bypass capacitor and to logic pins of the LTC held at VDD. AC and DC Disconnect AC and DC disconnect are two different methods of detecting whether a valid PD is present and requires power. AC disconnect is the default method for the DC98 but can be converted to DC disconnect in the midspan solution through two jumpers. Moving DISCON (JP) to DC will short the ACCOUT pin to VSS and configure the LTC to DC disconnect. Moving jumper setting for ACCOMP (JP) to DC bypasses the AC blocking diode and removes the RC used for AC disconnect from the main circuit. Legacy Detection LEGACY jumper JP controls whether legacy detect is enabled. If the LEGACY pin is held at VDD (EN selected), legacy detect is enabled and testing for a large capacitor is performed to detect the presence of a legacy PD on the port. If held at VSS (DIS selected), only IEEE 80.af compliant PDs are detected. If left floating (no jumper), the LTC enters force-power-on mode and any PD that generates between V and 0V when biased with 70μA of detection current will be powered as a legacy device. This mode is useful if the system uses a differential detection scheme to detect legacy devices. Warning: Legacy modes are not IEEE 80.af compliant.

5 Operating Principles Figure. DC98 Options

6 DC98A Layout Top Silkscreen Layer

7 DC98A Layout Layer Layer 7

8 DC98A Layout Layer Silkscreen Bottom 8

9 DC98B Layout Top Silkscreen Top Layer 9

10 DC98B Layout Bottom Layer Bottom Silkscreen 0

11 Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER DC98A- Required Circuit Components CPM CAP, XR, µf V, 0%, 00 MURATA, GRM8RC0KED C CAP, X7R, 0.µF V, 0%, 00 MURATA, GRM88R7C0KA0D C, C CAP, X7R 0.µF 00V, 0%, 00 MURATA, GRM88R7A0KAD D DIODE, SWITCHING, SOT DIODES INC, BAS9-7-F D DIODE, 8V TVS, SMA-DIODE DIODES INC, SMAJ8A- J JACK, POWER, RJ-JK0-0BNL PULSE, JK0-0BNL 7 LED, LED LED, GREEN, LED-ROHM, SML-00 ROHM, SML-00FTT8 8 L IND, PWR, 0000µH, L-COIL-DS08C COILCRAFT, DS08C-0MLC 9 RPM RES, CHIP.k /W %, 080 VISHAY, CRCW080KFKEA 0 R RES, CHIP k /0W %, 080 VISHAY, CRCW080K00FKEA R RES, CHIP k /W %, 00 YAGEO, RC00FR-07KL R RES, CHIP 0k /W %, 00 YAGEO, RC00FR-070KL U IC, LTCCS, SO LINEAR TECHNOLOGY, LTCCS Optional Circuit Components C CAP, X7R 000PF kv, 0 MURATA, GRBR7LA0KW0L C, C8, C, C CAP, X7R, 0.µF V, 0%, 00 MURATA, GRM88R7C0KA0D C CAP, ELECT,.7µF V, C-PANA-EEVFK-C PANASONIC, EEE-FKJR7R C7, C CAP, X7R, 0.7µF 00V, 0%, 080 MURATA, GRMBR7A7KA7L C9, C0 CAP, X7R 0.µF 00V, 0%, 00 MURATA, GRM88R7A0KAD D, D DIODE, SHOTTKY, PICO MINI, SOT CENTRAL SEMI, CMLSH0-7 D DIODE, 8V TVS, SMA-DIODE DIODES INC, SMAJ8A- 8 D DIODE, RECTIFIER A, SMB-DIDOE DIODES INC, SBB--F 9 D8, D7 DIODE, V, ZENER, SOD CENTRAL SEMI, CMDZL 0 J, J CONN, RJ- RIGHT ANGLE, RJ STEWART CONN SYS, SS-88-NF-K LED LED, YELLOW, LED-ROHM, SML-00 ROHM, SML-00YTT8 R, R8 RES, CHIP k /W %, 00 YAGEO, RC00FR-07KL R RES, CHIP.k /W %, 00 AAC, CR-JM R, R7 RES, CHIP 0k /W %, 00 VISHAY, CRCW000KJNEA SW SWITCH, PUSH BUTTON WÜRTH, 00 8 J SOCKET, X, 0.079", VERTICAL SAMTEC, SQT-0-0-LM-S-00 7 U IC, LTCCDE, DFNDE LINEAR TECHNOLOGY, LTCCS Hardware for Demo Board Only E, E, E9, E0, E TP, TURRET, 0.09" MILL-MAX, E, E, E, E, E7, E8 TP, TURRET, 0.0" MILL-MAX, JP, JP, JP, JP, JP, JP JMP, X, 0.079" SAMTEC, TMM-0-0-L-S 0 JP7 JMP, X, 0.079" OPT FOR JP TO JP ( and ) SHUNT, 0.079" CENTER SAMTEC, SN-BK-G J, J JACK, BANANA, KEY-7 KEYSTONE, 7-7 MH TO MH STANDOFF, SNAP ON, /" KEYSTONE, 88

12 Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER DC98B Required Circuit Components C, C CAP, X7R, 0.µF V, 0%, 00 MURATA, GRM88R7C0KA0D C, C CAP, X7R 0.µF 00V, 0%, 00 MURATA, GRM88R7A0KAD C CAP, X7R, 0.7µF 00V, 0%, 080 MURATA, GRMBR7A7KA7L D DIODE, 8V TVS, SMA-DIODE DIODES INC, SMAJ8A D DIODE, SCHOTTKY, PICO MINI, SOT CENTRAL SEMI, CMLSH0- J HEADER, X, 0.079", SMT, HORIZONTAL SAMTEC, MMT-0-0-S-SH-00 7 R RES, CHIP 0kΩ /W %, 00 AAC, CR-JM 8 R RES, CHIP kω /W %, 00 AAC, CR-0JM 9 U I.C., LTCCDE, DFNDE LINEAR TECHNOLOGY, LTCCDE

13 Schematic Diagram V-7V + J _ (EXTERNAL V SUPPLY OPTIONAL) VDD E VDD C E 0.UF VSS E D D C C VDD VDD VDD LEGACY MIDSPAN B ENFORCE CLASS B ENFCLS D SBB VDD ECO REV REVISION HISTORY DESCRIPTION APPROVED DATE PRODUCTION DILIAN R MIDSPAN PSE MIDSPAN OUT MIDSPAN IN VSS VSS J E SW SD D8 CMDZL V C 0.UF PM E PWRMGT JP LEGACY EN DIS JP MIDSPAN EN DIS E E PANASONIC EEVFKJR7R + C.7UF V R 0K R.K D7 CMDZL V R K D CMLSH0- JP ACCOMP MIDPSE LED GRN CPM UF E8 SD C 0.UF 00V R 0K D BAS9 L 0000UH DS08C-0 COILCRAFT E9 J SS-8-NF-K 7 8 CHS CHS U LTCCS C 0.UF 00V D SMAJ8A E7 LED VDD SD LEGACY MIDSPAN ENFCLS VSS VSS LED PWRMGT OSC 7 ACCOUT 8 OUT 0 OUT 9 R K RPM.K % 080 J SS-8-NF-K 7 8 CHS CHS EN DIS VSS JP E C 0.UF LED YELLOW C7 0.7UF 00V 080 AC DC JP DISCON JP PWRMGT EN DIS RJ RJ VOUT_MID LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; TECHNOLOGY Fax: (08)-007 HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T. LTC Confidential-For Customer Use Only VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL A NOTES: UNLESS OTHERWISE SPECIFIED APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. DILIAN R. TITLE: SCHEMATIC A CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR MAIN BOARD, SINGLE PORT AUTONOMOUS PSE TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.. ALL RESISTORS ARE IN OHMS, 00. ALL CAPACITORS ARE 00.. INSTALL SHUNTS ON JP-JP PINS AND. CUSTOMER NOTICE APPROVALS THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NONE SIZE N/A DATE: IC NO. REV. Friday, September, 0 SHEET OF 0 McCarthy Blvd. Milpitas, CA 90 Phone: (08)-900 LTCCS / LTCCDE DEMO CIRCUIT 98A

14 Schematic Diagram ENDPOINT PSE OPTIONS PM D D TO DAUGHTER CARD J LED PM TD+ CT TD- RD+ RD- VC+ VC- VC+ VC- X VO- GND PM E0 VOUT_EP U LTCCDE C C C8 0.UF VDD SD LEGACY MIDSPAN ENFCLS VSS VSS HDX-079 LED PWRMGT OSC 7 ACCOUT 8 OUT 0 OUT 9 OUT TO PD ENDPOINT PSE B B OPTIONAL ENDPOINT PSE LAYOUT C 0.UF C9 0.UF 00V 00 R8 K D CMLSH0- R7 0K C 0.7UF 00V 080 ENDPSE LED GRN R K 080 D SMAJ8A 0 J VO- C 000PF,KV HDX-079 TO PHY GND CHS JK0-00 JP7 OPT CHS C0 0.UF 00V 00 0 CUSTOMER NOTICE APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; TECHNOLOGY Fax: (08)-007 HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T. LTC Confidential-For Customer Use Only VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL A APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. DILIAN R. TITLE: SCHEMATIC A CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR MAIN BOARD, SINGLE PORT AUTONOMOUS PSE TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NONE SIZE N/A DATE: 0 McCarthy Blvd. Milpitas, CA 90 Phone: (08)-900 LTCCS / LTCCDE DEMO CIRCUIT 98A IC NO. REV. Friday, September, 0 SHEET OF

15 Schematic Diagram Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

16 DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 0 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 0 McCarthy Blvd. Milpitas, CA 90 Copyright 00, Linear Technology Corporation LT PRINTED IN USA Linear Technology Corporation 0 McCarthy Blvd., Milpitas, CA (08) -900 FAX: (08) LINEAR TECHNOLOGY CORPORATION 0