Very Large Scale Integration (VLSI)

Transcription

1 Very Large Scale Integration (VLSI) Lecture 8 Dr. Ahmed H. Madian ah_madian@hotmail.com

2 Content Array Subsystems Introduction General memory array architecture SRAM (6-T cell) CAM Read only memory

3 Introduction Memory Arrays Random Access memory Serial Access memory Read/write memory (RAM) Read only memory (ROM) Content addressable memory (CAM) Queues Shift registers (volatile) (non - volatile) Static RAM (SRAM) Dynamic RAM (DRAM) Last In First out (LIFO) First In First out (FIFO) Parallel In Serial out (PISO) Serial In Parallel out (SIPO) Mask Rom Progrmmable ROM (PROM) Erasable Electrically Programmable Flash Rom Erasable ROM Programmable (EPROM) ROM (EEPROM)

4 Design Tradeoffs Density: bits/unit area. Usually higher density also means lower cost per bit. Improvements due to finer lithography, better capacitor structures, new materials with higher dielectric constants. Improvements in one dimension come at an increased cost in the other dimensions. Speed: access time (latency) and bandwidth. Improvements due to better sensing (smaller voltage swing), increased parallelism (overlapped accesses), faster I/O. Power consumption: want power to depend on access pattern not quantity of bits stored. Improvements due to lower supply voltage.

5 Memory Array architecture Why we need a column decoder?

6 Memory Array (cont.) Typically want an aspect ratio that is not too far from square How to divide up the row, column address decoding? Use an 8K x 32 SRAM = 256 Kb = = 2 9 rows x 2 9 columns Row decoder is 9 to 512 decoder Every 32 (2 5 ) columns is a word, and we only need to decode words. So, column decoder needs to decode 2 4 words, so need a 4 to 16 column decoder.

7 6-transistor SRAM cell 6-T cell needs a careful and clever layout to achieve good density

8 6-T SRAM cell (cont.) Sense amplifier is used to detect any small changes between the bit line and its complement

9 6-T SRAM cell (cont.) Only one control terminal for access Word-line Read Both bit lines start at V DD Cell pulls one down Cell value remains unchanged Write One bit line is pulled low Low bit line value over-powers cell Cell changes state

10 Bit-line vs. word-line Assertion of word-line accesses all cells in a row Not all bits that are read from a row may be used. Loading on word line is high Bit lines connect all cells in a column, only one cell in a column can ever be on at a time Would like to keep bit-line swing low in order to preserve power Sense Amp function is to detect bit line change and produce a full 0 or 1 for output latch

11 Write circuitry

12 Bit-line biasing (cont.) Method I: Similar to pseudo nmos Permanent pull-up Still need to equalize! Swing is now "clamped" to V=I drive R pmos Sense amplifier must still operate around V DD

13 Bit-line biasing (cont.) Method II: "nmos" Swing is clamped and levels are shifted by V THn

14 Bit-line biasing Bit lines are typically biased somewhere between 0 and V dd improve speed of cell for reading/writing limit bit-line voltage swing for power savings Bit line biasing circuit at top of each column Bit line biasing circuit can either be static or dynamic (dynamic operation controlled by clock or pulse generated by address line change).

15 Read Delay How do we get high-speed operation? Parasitic delay of this gate (cell driving bit-line) is large Changing the transistor sizes doesn t help! (much) Parasitic delay changes only slowly with sizing (wire cap) Memory area will grow with larger transistor Needs to be small to get good density

16 How to Speed up Read? Use very short bit-lines 16 to 32 cells might be ok Use small swings Remember: t = C V/I Why does that help? C load V load is the charge we have to supply to the load Having smaller V load is equivalent to having smaller C load

17 Small Swings Cause two problems: How to generate them? How to sense them? Creating small swings Clamp the bit-line swings Make the word-line a pulse Just sense the bit-lines early Need to reset bit-lines to make sure both start high for read Sensing small swings Need low noise sensitivity implies differential inputs Need to build an amplifier.

18 Word selection Column decoder is similar to word-line decoder Need to select 1 out of 2 m columns for read/write

19 Word selection (cont.) Need transmission gate for column select nmos good for pulling Bit-line low (write) pmos good for passing voltage near V DD to sense amplifier (read)

20 Word selection (cont.) Possible to split signal path and make column signals unidirectional nmos for pulling word-line low (write) pmos for passing voltage near VDD to sense amplifier (read) More wires, but they are shorter Puts large write driver parasitics on already loaded bit-lines Not at sense amp input

21 Sense amplifier Only one bit line will swing. Want Sense Amplifier turned on for short amount of time in order to save power. Job of SA is to sense bit line swing, amplify to full swing output.

22 Sense amplifier sharing

23 4 to 1 tree decoder Are able to use nmosonly pass transistors because of limited swing. Number of pass transistors in series is a concern, but limited swing helps speed.

24 Decoders

25 Decoders (cont.) Increasing number of input lines increase the area of the decoder

26 Pre-decoding Decoders with many inputs can be formed from cascade of smaller gates. This technique is called pre-decoding

27 Bit line to bit line coupling

28 Transposed Bit lines Does not reduce noise coupling, but couples same noise into both bitlines so appears as common node noise and is rejected.

29 Content addressable memory (CAM)

30 Dynamic Memory Cell

31 Dynamic Ram (cont.) Voltage swing on Bitline is small Want Bitline capacitance as small as possible, Bit cell capacitance as large as possible to increase charge transfer Read is destructive part of read cycle is used to restore level inside of bit cell capacitor Capacitor leaks, must be refreshed periodically Noise sources in DRAM are word line to bit line coupling, bit line to bit line coupling

32 Read Only Memory (ROM)

33 Mask-programmed ROMs Y 0 Y 1 Y 2 Y 3 Y 4 =00101

34 Programmable ROMs PROM can be fabricated as ROM fully populated with pull-down transistors in every position. Each transistor is placed in series with a fuse made of polysilicon, or any other conductor that can be burnt out by applying a high current. PROM is one time programmed

35 EPROM, EEPROM and Flash Reprogrammable nonvolatile memory. These memories use a second layer of polysilicon to form a floating gate between the primary gate and the channel The floating gate is a good conductor, but it is not attached to anything. Applying a high voltage for the upper gate causes electrons to jump through the thin oxide onto floating gate through the processes called avalanche injection. Injecting electrons includes a negative voltage on the floating gate, which increasing threshold voltage of the transistor to the point that it is always OFF. Gate Polysilicon Floating gate source n+ Drain n+

36 Assignment 4 It would be available on web today the due date Tuesday, 15/12/2009 Quiz 2 will be next week