Algorithmic Memory Increases Memory Performance By an Order of Magnitude

Transcription

1 Algorithmic Memory Increases Memory Performance By an Order of Magnitude Sundar Iyer Co-Founder & CTO Memoir Systems Track F, Lecture 2: Intellectual Property for SoC & Cores May 2,

2 Problem: Processor-Embedded Memory Performance Gap Normalized Growth Performance degradation can be more significant and is getting worse! Processor Embedded Memory Performance Gap 1 * Source: Hennessy and Patterson, 5 th Edition May 2,

3 Why is Embedded Memory Slow? clk read addr data A B C D E F G H A B C D E F G H One operation per memory clock cycle How can we increase memory performance without increasing memory clock speed? May 2,

4 Solution: Algorithmic Memory = Memory Macros + Algorithms Physical Memory 500 MHz 1P 1P 1P 1P Algorithmic Memory 500 MHz 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P 1P Extra Memory 500 MHz Allows 500 Million MOPS 1 ( 1 Memory Operations Per Second) 500 MHz Allows 2000 Million MOPS More Ports, Same Clock May 2,

5 Solution Overview 2X Performance for ~15% area overhead RTL Based: No Circuit or Layout changes Any Embedded Physical Memory 1P 1P 1P 1P 1P 1P 1P 1P Simultaneous Accesses to the same Address, Row, Column, or Bank (no exceptions) 1P 1P 1P 1P Extra Memory Algorithmic Memory Each Port can access the entire Memory Address Data Addr Data Addr Data Addr Data Addr Exhaustively Formally Verified & Transparent to end-user Using Physical 1-Port Memory to Build any Multiport Functionality May 2,

6 Usage & Adoption Easily Interface Presents standard memory interface Adds no clock cycle latency Used as a drop-in replacement Readily Integrate Fits seamlessly in SoC design flow Used in SoCs - ASICs, ASSPs, GPPs Rapidly Implement Supports any process, node or foundry 8K Depth 128 Width Physical Memory Memoir IP IP A D A D A D A D Identical Pinout to Standard Memory May 2,

7 Increases Density Denser Physical 1P Memory Algorithmic 2P Memory Physical 2P Memory Normalized for 1P = 1 Mb/mm2 May 2,

8 Increases Density Normalized for 1P = 1 Mb/mm2 May 2,

9 Reduces Total Power Based on 40nm example May 2,

10 Reduces Total Power Based on 40nm example May 2,

11 Configurable Performance Performance (MOPS) Higher performance algorithmic memories 4P 2P Higher density algorithmic memories Memory Density (Mb/mm2) Power efficient algorithmic memories Algorithmic 2P SP SP Physical Memory Higher Performance Algorithmic Memory Area Efficient Algorithmic Memory Power Efficiency (Mb/mW) Power Efficient Algorithmic Memory May 2,

12 Increases Portfolio of Available Memories 1R/4W 1R1W 2R/1W 4R/1W 1R/2W 3R1W 1RW 2RW 2R2W 1R2W 1R3W 3R/1W 2R1W Physical Memory Algorithmic Memory May 2,

13 Rapid Memory Analysis & Generation 2X 3X 4X Push Button Analysis # Read # Write Generate Memory Real-time Algorithmic # Specify Width Capacity Feed Inputs GEN GUI SYN CHK Memory Memory # Depth Reduced Standard Acceleration Ports Latency Feedback Power Area Optimization SRAM edram Register File Standard Cell Library & Building Blocks May 2,

14 Multiport Memory Usages 3R1W 2R1W Descriptor and Free Lists, Ingress Buffers L2 MAC Lookups, Shared Caches 1R2W 1R3W 2R2W 1R1W Descriptor and Free Lists, Egress Buffers Cache Coherency Arrays for L2/L3 Caches Netflow, Counters State Tables, Linked Lists 4Ror1W Data and Tag Arrays for L2, L3 Caches 3Ror1W 2Ror1W Route Lookup Tables ACL Tables May 2,

15 Exhaustive Formal Verification Reduces Risk Independently Verify Logic Mathematically proven algorithms Formally, exhaustively verified RTL SRAM BIST Wrapper SCAN Separately Test Physical Memories Supports 3 rd party DFT methodology Transparent customer BIST, BISR BIST Physical Memory Algorithmic Memoir Memory IP Doesn t need complex multiport BIST A D A D A D A D May 2,

16 Tier-1 OEM Evaluation Performance, Area and Power Benefits Large ASIC Algorithmic Memory Solution 4X MOPS Memories 24mm 21mm Area 576 mm 2 24mm 800 Mb of total memory 165 Memory Instances Versatile memories required 4R/1W, 2R1W, 1R2W memories Area 441 mm 2 21mm Area Savings of 135 mm 2 (23% die) 136 Memory Instances Accelerated Power Savings > 12W 4X MOPS for select memories May 2,

17 Summary 1. Increases Port and Clock Performance 2. Lowers Area and Power 3. Easy Interface, Integration and Implementation 4. Creates Versatile Memory Portfolio 5. Reduces Cost, Risk and Time to Market Algorithmic Memories are not a panacea, but present a new solution to alleviate the processor embedded memory performance gap May 2,

18 Q & A Sundar Iyer sundaes@memoir-systems.com Come Visit Our Booth! Memoir Systems May 2,