Embedded Quality for Test. Yervant Zorian LogicVision, Inc.

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1 Embedded Quality for Test Yervant Zorian LogicVision, Inc.

2 Electronics Industry Achieved Successful Penetration in Diverse Domains

3 Electronics Industry (cont( cont) Met User Quality Requirements satisfying users to buy products again Created an Unprecedented Dependency - market-driven product Users Competitors Electronic Product

4 Quality Requirements at Chip Level Manufacturing Test for Chips To achieve board defect levels < 1% To maintain ATE cost Diagnostics for Chip Manufacturing To enable physical failure analysis To enhance yield by enabling repair for large memories

5 Quality Requirements at Board Level Board Level Manufacturing Test Full Coverage of board level defects Chip failures (handling, stress, infant mortality) Diagnostics for Board Level Manufacturing To determine failed interconnect or chip To enable speedy repair

6 Conventional Test Flow Functional Patterns Deterministic ATPG with Scan Path Full Pin Count Automatic Test Equipment

7 Emerging Electronics Industry Products Shift to Communications and Connectivity Maintain competitive edge by providing: Greater Product Functionality Lower Cost (product life cycle) Reduced Time-to-Profitability Higher Quality and Reliability

8 Emerging Infrastructure The internet runs on silicon. Andy Grove The information superhighway is paved in silicon. Scott McNealey

9 Emerging Industry Trends Caused new technologies: Greater Complexity Increased Performance Higher Density Lower Power Dissipation

10 The Key Challenge To meet Users Quality Requirements for new Technologies To assure New Products are adequately: Tested, Verified, Measured, Debugged, Repaired,...

11 Emerging New Challenges Observe Implications on Product Realization Analyze Existing Quality Assurance Approaches Identify Challenges Demonstrate Potential Solutions Design Manufacturing Diag. & Yield Field Service

12 Design Challenge: Quality Implication: # of Transistors per pin (Testing Complexity Index) increased internal speed vs external Testing Complexity Index - [#Tr. per Pin] 1.60E E E E E E E E+ 0 Implications of SIA Roadmap: Testing Year F. Size [mm] Source: W. Maly, 1996 Source: SIA Roadma Design Manufacturing Diag. & Yield Field Service

13 Design Challenge: Quality Leverage Internal Bandwidth vs External Bandwidth System-on-Chip ASIC I/O Drivers off-chip bus 32-bits I/O Drivers DRAM ASIC on-chip bus 128/512-bits DRAM

14 Design Challenge: Quality External Bandwidth max bits of data/time from ATE to IC Internal Bandwidth max bits of data/time from on- chip test resource to embedded core Bandwidth Gap Bandwidth Gap Y1995 Y1998 Y2001 Y2004 Y2007 Y2010 Internal Bdw. (Capacity*IntFreq External Bdw (IO*ExtFreq)

15 Design Challenge: Quality External Test Data Volume can be extremely high (function of chip complexity) Requires deep tester memory for scan I/O pins Slow test throughput with long scan chains, especially for core-based designs External Test Super Tester Pattern Generation Precision Timing Diagnostics Power Management Test Control Very high pin count Deep memory Slow throughput Memory Logic. Mixed- Signal I/Os & Interconnects

16 Design Challenge: Quality Solution: Dedicated Built-In H/W for embedded test functions Repartition tester into embedded test and external test functions Include low H/W cost and high data volume embedded-quality for test External Test Standard Digital Tester Limited Speed/ Accuracy Low Cost-per-Pin Embedded Test (Built-in) Pattern Generation Result Compression Precision Timing Diagnostics Power Management Test Control Support for Board-level Test System-Level Test Memory Logic. Mixed- Signal I/Os & Interconnects Chip, Board or System Source: LogicVision

17 Design Challenge: Quality Source/ Sink Source/ Sink Test Access Scan Paths External Test External Test Embedded Test Source/ Sink High- Bandwidth Source/ Sink Source/ Sink Low - bandwidth High bandwidth External Test Embedded Test External Test Embedded Test

18 Design Challenge: TTM Implication: Emergence of reusable core-based design Multiple hardware description levels (hard, soft, firm) Standard IC functions (library elements) and legacy cores Source: VSI Alliance

19 SOC Market Growth 30 Worldwide Revenue (Billions of Dollars) Source: Dataquest

20 Paradigm Shift in SOC Design System on a Chip System on a board

21 Design Challenge: TTM SOC manufactured and tested in single stage Core I/Os often more than Chip I/Os Test generation difficult due to limited core design knowledge Direct access to core ports unavailable Core & UDL test part of System-On-Chip test System-on-Board (SOB) Process IC Design IC Manuf. IC Test SOB Design SOB Manuf. SOB Test ASIC Design ASIC Manuf. ASIC Test System-on-Chip (SOC) Process Core Design UDL Design SOC Integration SOC Manuf. SOC Test

22 Design Challenge: TTM Built-in dedicated H/W to create autonomous internal core test Built-in dedicate System- On-Chip test optimization Built-In standard core test interface for each core

23 Design Challenge: TTM IEEE P1500 (9/96) develops a standard for embedded core test interface comprised of: Standard Core Test Information Model (CTL) using a Standard Description Language (STIL) Standard Core Test Wrapper and Control Mechanism Phase 1: Dual Compliance for Digital Cores (1149.1) Phase 2: Analog Cores (1149.4), Testability Guidelines VSI Manufacturing Test Related DWG supports IEEE P1500 standardization

24 Design Challenge: TTM BIST Enabled Core TP Glue Logic BIST Enabled Core TP M BIST Memory BIST M BIST Boundary Scan Chain Logic BIST BIST Enabled Core TP Glue Logic Logic BIST BIST Enabled Core TP Boundary Scan Chain M BIST M BIST Logic BIST Logic BIST Logic BIST TAP TDI TCK TMS TRST TDO

25 Design Challenge: Quality Implication: Increased chip internal speed (ASSP with 200MHz+, Microprocessors with 1 GHz+) Multiple and overlapping clock domains Multi-cycle data paths Complex clock distribution Recent SEMATECH study revealed criticality of performance faults

26 Design Challenge: Quality High speed ATE substantially more expensive ATE vs Chip Technology discrepancy: Tester uses 5 year old technology - chips move to next generation every 2 years ATE accuracy degrading: Chip cycle time will crossover ATE accuracy Time in ns, Yield loss in % device speed (ns) projected yield loss (%) 1 ATE OTA(nS ns)

27 Design Challenge: Quality Solution: Built-In dedicated H/W to run Built-In Self-Test at-speed and detect performance faults Major move for mainstream systems to implement at-speed BIST for production test Source: Sun Microsystems

28 Manufacturing Challenge: Test Cost Embed in a single chip: Logic, Analog, DRAM blocks Embed advanced technology blocks: FPGA, Flash, RF/Microwave Beyond Electronic blocks: MEMS Optical elements Logic Core Memory µp Logic Memory Logic Mixed Signal Memory Logic Design Manufacturing Diag. & Yield Field Service

29 Manufacturing Challenge: Test Cost W(5FB 8A3) R(4C2 9E0) Logic W(5FB 8A3) R(4C2 9E0) Functional Tester Logic µp Mixed Signal Mixed-Signal Tester W(5FB 8A3) R(4C2 9E0) Core Memory Logic W(5FB 8A3) R(4C2 9E0) Logic Tester Memory Memory Logic Memory Tester Multiple Insertions or Super ATE!

30 Moore s Law for Test Cost of Silicon Mfg and Test Si capital / transistor Test capital / transistor cost: cents /transistor Based on SIA Roadmap Data

Manufacturing Challenge: Test Cost JTAG 4 Pin Interface Low Cost Sort Machine with gicvision BIST Access Software Logic µp Logic Mixed Signal I/O s

31 Manufacturing Challenge: Test Cost JTAG 4 Pin Interface Low Cost Sort Machine with gicvision BIST Access Software Logic µp Logic Mixed Signal I/O s tri-stated no critical timing Core Memory Logic If full scan already exists hen the dues are already paid Memory Memory Logic LogicVision s Embedded Test

32 Manufacturing Challenge: Quality High Density Chips: Advanced Semiconductor Technology with very high density number of millions of transistors per sq. cm. will increase by a factor of three in next five years Test Escape due to unmodeled faults (ex: SOI process, Copper Interconnect) Use built-in dedicated h/w to execute fault model independent pseudo-random pattern based test

33 Manufacturing Challenge: Quality Challenge: High performance board and MCM applications (ex: 500MHz chip-to-chip) Require Chip-to-Chip Interconnect test for static and dynamic faults Source: Stratus Computers

Manufacturing Challenge: Quality Solution: IEEE 1149.

34 Manufacturing Challenge: Quality Solution: IEEE Boundary- Scan for static faults At-Speed Interconnect Test requires Built-In dedicated H/W Source: Stratus Computers

Diagnosis & Yield Challenge: Cost Implication: Large Embedded: SRAM, DRAM, Flash Beyond certain size memories necessitate redundancy/repair during

35 Diagnosis & Yield Challenge: Cost Implication: Large Embedded: SRAM, DRAM, Flash Beyond certain size memories necessitate redundancy/repair during manufacturing test (and field reliability) Requires Logic ATE, Memory ATE, Laser Repair Equipment, and Redundancy Analysis Design Manufacturing Diag. & Yield Field Service

36 Diagnosis & Yield Challenge: Cost Two reconfiguration strategies: 1. Hard: Built-in dedicated h/w for Redundancy Analysis and external repair (fuse blow) 2. Soft: Built-In dedicated reconfiguration mechanism using BISR (test repeatability) Adopted by several chip manufacturers WAFER Memory test Analysis & Reconf Memory retest Logic test (wafer) Packaging Logic test (package) Pass/Fail Testing/Repair of ASIC with Large Embedded Memory Memory Repair

37 Diagnosis & Yield Challenge: TTM Advanced Packaging Technologies Increased use of Flip-Chip Technology: Flip-Chip design dedicates a metal layer for area array interconnects (Direct Chip Attach, Chip Scale Packaging, BGA and MCM) Increased use of Fine-Pitch Technology: probing limitations due to miniaturized package technologies (FC, CSP) -> very expensive probe cards Increased use of bare die usage -> inadequacy of conventional package test (Direct Chip Attach, MCM)

38 Diagnosis & Yield Challenge: TTM Conventional failure mode analysis based on E-beam can not be used with flip-chip Solution: Use Embedded Quality functions for diagnosis: stop-on-error, data logging for memories, and scan-based diagnosis for random logic. This can be leveraged for interactive at- speed diagnosis. Flip-chip die

39 Diagnosis & Yield Challenge: TTM Conventional failure mode analysis based on E-beam can not be used with flip-chip Solution: Use Embedded Quality functions for diagnosis: stop-on-error, data logging for memories, and scan-based diagnosis for random logic. This can be leveraged for interactive at- speed diagnosis. Flip-chip die

40 Diagnosis & Yield Challenge: TTM Source HPL, Inc

41 Diagnosis & Yield Challenge: TTM Source HPL, In

42 Field Challenge: Quality Challenge: Increase Impact of Cosmic Radiation on Sea Level Solutions: Embedded test dedicated h/w function for On-line BIST to detect transient (soft) errors Design Manufacturing Diag. & Yield Field Service

43 Field Challenge: Cost, TTM Design and Manufacturing of Complex Boards and Systems costs too much and takes too long Test development cost is 35% of total product development time Test, Diagnosis and Repair cost for complex systems reaches 40-50% of total product realization cost

44 Hierarchical Embedded Test OS / Software Interface (accessible by network) at the Application layer Service Kernel Software Operating System and Applications ATE / Hardware Interface (accessible by connector) for Manufacturing or Field EQ Hardware EQ EQ Box Board SOC Reuse of dedicated built-in quality hardware Source: LogicVision

45 Field Challenge: Cost, TTM Leveraging dedicated Embedded Quality function drastically reduces test development interval and test costs Without Built-In Quality With Built-In Quality 29.4 % % Test Cost as % of Total Life Cycle Cost Source: AeroSpace Study

46 Conventional Quality Paradox Design Test Management Manufacturing Test Management It is really not my problem, but I will do what I can to help out. I have little control on the design process! I will buy the best testers possible and perform as much testing as possible to ensure the expected quality.

47 Test Resource Partitioning External ATE DFT Methods Logic Tester Memory Tester Mixed Signal Tester Processor Tester Board Tester Embedded Test H/W Automation Tools Test Programs Diagnostic Data Scan Design Isolation & Access Random Pattern BIST Algorithmic BIST TAP/BSCAN A Solution that Combines the Best of DFT and ATE

48 Conclusions To ensure quality of electronic products using emerging technologies: Embedded Quality functions are added into the high level designs of embedded cores, SOCs,, board and systems A range of Embedded Quality functions provide adequate test, verification, diagnosis, debug, measurement and repair Design Manufacturing Diag. & Yield Field Service

49 Thank YOU for your attention

Testable SOC Design. Sungho Kang

Testable SOC Design. Sungho Kang Testable SOC Design Sungho Kang 2001.10.5 Outline Introduction SOC Test Challenges IEEE P1500 SOC Test Strategies Conclusion 2 SOC Design Evolution Emergence of very large transistor counts on a single