A Fast Synchronous Pipelined DRAM Architecture with SRAM Buffers

Transcription

1 A Fast Synchronous Pipelined DRAM Architecture with SRAM Buffers Chi-Weon Yoon, Yon-Kyun Im, Seon-Ho Han, Hoi-Jun Yoo and Tae-Sung Jung* Dept. of Electrical Engineering, KAIST *Samsung Electronics Co., Korea Semiconductor System Lab 1

2 Outline Motivations Related Works SP-DRAM Architecture Simulation Results Conclusions Semiconductor System Lab 2

3 Motivations Key Features of DRAM Latency & Peak Bandwidth Latency Row Access DRAM Core Depends on Physical Characteristics Column Access Bus Access S/A Interface Bandwidth Bus width * I/O Freq. EDO, SDRAM, DDR, D-RDRAM Semiconductor System Lab 3

4 Motivations Today s Computer System Random Access Pattern on System Memory Processor Access Patterns become more ramdom Long Latency frame buffer System Memory UMA Graphic accelerator Bridge Texture Memory Serious degradation of Overall System Performance PCI Semiconductor System Lab 4

5 Related Works Multi Bank Structure 1994, MoSys Same problems for the same bank access Small Block access with Address Non-Multiplexing FCRAM (Y. Sato, Fujitsu, SOVC 98) Backward Compatibility Temporal Storage Buffer S. Wakayama, Fujitsu, SOVC 98 Feasibility Integration of SRAM EDRAM, CDRAM (1992, Mitsubishi), VCM(1998, NEC) Data Locality Improve effective BW Limited to the latency of Cell Core Semiconductor System Lab 5

6 SP-DRAM Architecture EDRAM CDRAM VCM SP-DRAM Focussed on Latency DRAM EDO DRAM SDRAM Rambus DRAM (Base) DDR DRAM SLDRAM Direct Rambus Focussed on Bandwidth Semiconductor System Lab 6

7 Features of SP-DRAM Key Features of SP-DRAM Multiple SRAM Buffer Structure Reduce the latency by Utilizing the Access Locality Apply Same interface with that of Conventional SDRAM Pipeline Scheme at Row Path Latches & Data Buffers Accelerates the Successive Cell Core Accesses Partial Activation Sub-Wordline Scheme at Cell Core Eliminates unnecessary Data Sensing Operations Semiconductor System Lab 7

8 SP-DRAM Overview 1st Stage Segment 2nd Stage Row Addr. Buff. Row Addr. dec. Latch MWL Driver SWL Driver Cell Core S/A Col. Addr. Buff. Col. Addr dec. Segment Row Buffer SRAM Buffers (Channels) X n 3rd Stage Semiconductor System Lab 8

9 SRAM Buffer SRAM Buffer Structure Conventional SRAM Cell Segment Easy to Adapt Conventional Interface DRAM Cell Core (Row Data buffer) Segment Row Dec. for SRAM SRAM Buffer Stack Dout Interface CD0 CDn Semiconductor System Lab 9

10 Pipeline Operation 3-Stage Pipeline Timing Diagram 3-stage Pipelining Zero trcd Zero trcd Row Cycle Address Row Col Row Col SWL MWL Cell Core Ops. Address Data Transfer Cell Core Operations (Sensing, Precharge, etc.) Address Data Transfer Sensing & Restore Semiconductor System Lab 10

11 Partial Activation Scheme Partial Activation by Sub-Wordline Scheme Col. Addr Seg_En MWL Rx Rx Rx SWL Row Addr. Segment Semiconductor System Lab 11

12 Cell Core Architecture Cell Core Architecture Sub-Block Array Alternate Shared Sense Amp 64cell 64cell 64cell 64cell 100MHz Clock 0.35 µm DRAM Tech. 64cell 64cell 64cell 64cell Semiconductor System Lab 12

13 Layout of Cell Core Semiconductor System Lab 13

14 Simulation Results Data Transfer from Cell Core to SRAM Semiconductor System Lab 14

15 Row Cycle Comparisons The Successive Read Accesses (Best Case) Read(100MHz, BL = 4, Same bank Access) SDRAM DATA RAS CAS PRE RAS CAS D0 D1 D2 D3 D0 11 Cycles VC-SDRAM ACT PFR ACT PFR 9 Cycles DATA D0 D1 D2 D3 D0 D1 D2 D3 SP-DRAM Precharge ACT PFR ACT PFR 6 Cycles DATA D0 D1 D2 D3 D0 D1 D2 D3 Semiconductor System Lab 15

16 Memory System Performance Analyzer (POPeye) Processor Performance Analyzer POPeye Application Programs OS : windows95 Memory Virtual PC Emulator (a) High Level Memory System Performance Analyzer Floppy Disk L2 Cache Tag Hard Disk Cntl Tag Cntl TIO[7:0] Bus Controller Memory controller (cache contr.) DRAM interface Host Bus 66MHz Main Memory PCI Bus 33MHz KeyBoard Mouse BIOS (b) Target System Architecture Yon-Kyun Im, et al, POPeye : A System Analysis Tool for DRAM Performance Measurement, ICVC 99, VL-P18 Semiconductor System Lab 16

17 Performance Comparisons SDRAM VCM SP-DRAM PhotoShop 3.0 MSexcel 7.0 MSword 7,0 Semiconductor System Lab 17

18 Conclusions SP-DRAM Architecture Multiple SRAM Buffer Structure 3-Stage Pipeline Scheme in Row Path Partial Activation Scheme in Cell Core Features Fast Row-cycles Low Power consumption Backward Compatibility with Conventional DRAM Interface Performance 40% Faster than SDRAM 20% Faster than VCM Semiconductor System Lab 18