RECORD OF REVISION. Revision Date Page Contents. 2004/12/01 - New Release APEX DISPLAY CO., LTD. 2

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2 RECORD OF REVISION Revision Date Page Contents 24/12/1 - New Release APEX DISPLAY CO., LTD. 2

3 1 FEATURES (1) This module is 4 Color:Main (Blue)+Icon(Green+Red+Yellow). (2) This module is consist of 96x64 pixel dots OLED panel and Driver IC part mounted on a film using TCP(Tape carrier Package). OLED panel connecting with TCP via ACF process. (3) If necessary, Electrical components are mounted on a FPC(Flexible Printed Circuit) and FPC is connected to TCP film output interface in accordance with customer s request. (4) The Polarizer including anti-reflective layers is laminated on surface for improving the contrast ratio of OLED module. (5) Application : This display module will be used in a cellular phone (6) Driver IC : SSD133 (7) Input data : 8-bit 68/8-bit 88 SPI Interface. 2 NUMBERING SYSTEM AX C - _ No Code Value Description Remark T TN H HTN S STN yellow-green G STN Gray B STN Blue(Negative) 1 F FSTN LCD type C STN-color A A-TFT L Ltps-TFT O OLED P PLED 2 C Character-COB Display type D Character-TAB E Character-COG F Character-COF G Graphic-COB APEX DISPLAY CO., LTD. 3

4 H Graphic-TAB K Graphic-COG L Graphic-COF A Reflective type / 6: view B Reflective type / 12: view C Transflective type / 6: view D Transflective type / 12: view E Transmissive type / 6: view 3 Polarizer / Viewing Angle F Transmissive type / 12: view G Negative type / 6: view H Negative type / 12: view I Negative type / 3: view O Others None None backlight L LED array 4 Q LED edge Backlight type E EL C CCFL None Without backlight A Amber B Blue G Green L Yellow 5 O Orange Backlight color R Red Y Yellow-green W White F OLED&PLED FULL Color M OLED&PLED Area or Normal color 6 N Normal temperature type LCM temperature type H Extended temperature type 7 ~99 Version code APEX DISPLAY CO., LTD. 4

5 3 MECHANICAL DATA ITEM VALUE UNIT Number of Dot dots Panel Dimension 28.74(W) 22.2(H) 1.6max.(T) mm Active Area 2.135(W) (H) (.96 inches) mm Dot Size.185(W).185(H) mm Dot Pitch.21(W).21(H) mm Color Arrangement 4 color : Main(Blue)+Icon(Green+Red+Yellow) Module Size 28.74(W) 36.55(H) 1.6max.(T) mm Interface 8-bit 68/8-bit 88/SPI Interface APEX DISPLAY CO., LTD. 5

6 4 ELECTRONIC UNIT 4.1 Maximum Ratin g s Symbol Parameter Value Unit VDD V Supply Voltage Vcc V V_coMH Supply Voltage/Output Voltage V -- SEG/COM output voltage V VIN Input Voltage VSS VDD+.3 V TA Operating Temperature Range -2+7 C Tstg Storage Temperature Range -4+8 C Note: Voltage Reference To Vss 4.2 DC Electrical Characteristics Symbol Parameter Test condition Min Typ Max Unit Vcc Operating Voltage V VDD Logic Supply Voltage V Vox High Logic Output Level Iout=3uA,3.3MHZ..9*VDD -- VDD V VoL Low Logic Output Level Iout=3uA,3.3MHZ --.1* VDD V VIH High Logic Inpout Level Iout=3uA,3.3MHZ.8* VDD -- VDD V VR Low Logic Inpout Level Iout=3uA,3.3MHZ --.2* VDD V I CC,SLEEP Sleep Mode Current VDD=2.7V,Display OFF, No Panel attached ua I DD,SLEEP Sleep Mode Current VDD=2.7V,Display OFF, No Panel attached ua Note:(1. Unless otherwise specified Voltage Referenced to VSS,VDD=2.4 to 3.5V,TA=25 C 4.3 AC Electrical Characteristics (Unless otherwise specified, Voltage Referenced to VSS,VDD=2.4 to 3.5V,TA=25 C) Symbol Parameter Test condition Min Typ Max Unit Fosc Oscillation Frequency of Display Timing Generator VDD=2.7V KHz FFRM Frame Frequency for 64 MUX Mode 132x64 Graphic DisplayMode,Display ON,Internal Oscillator Enabled -- FOSC X 1/(DxKx64) -- Hz APEX DISPLAY CO., LTD. 6

7 4.4 Electro-Optical Characteristics Item Condition Min. Typ. Max. Unit Brightness I (a) Dark room 3 45 cd/m 2 Brightness II (b) Dark room 5 65 cd/m 2 Contrast Ratio Bright/Dark ( Dark room 2(at 45cd/m 2 ) (a), (b) CIE CIEx (Blue) Dark room CIEy (Blue) Dark room CIEx (Yellow) Dark room CIEy (Yellow) Dark room CIEx (Green) Dark room CIEy (Green) Dark room CIEx (Red) Dark room CIEy (Red) Dark room Life Time (d) Brightness I (a) 5 8 hrs Brightness II (b) hrs Sleep Mode (e) 1.5 mw NC Power Consumption Normal Type (f) 35 mw Condition: (a) Brightness I=45cd/m 2, VDD=3.3V, VCC=13V, R1=1M Contrast Control Register (81H): A[7:]=2CH. Pre-charge period (D9H): A[7:]=22CH. VCOM Deselect Level (DBH) : A[6:]=35CH. Display Clock Divide Ratio/Oscillator Frequency (Default). (b) Brightness II=65cd/m 2, VDD=3.3V, VCC=13V, R1=1M Contrast Control Register (81H): A[7:]=DFH. Pre-charge period (D9H): A[7:]=22CH. VCOM Deselect Level (DBH) : A[6:]=35CH. Display Clock Divide Ratio/Oscillator Frequency (Default). (C) Contrast Ratio=(Brightenss of the selected spot/brightness of the unselected spot.) (d) Lifetime : The period of time that the initial luminance decay 5% under the condition of continuous driving in all pixel on. (e) Sleep mode command is (AEH) (Display off). In the mode,can t be written data. (f) The OLED module operate as below condition : 25% pixel on,dc/dc CON. Off and 65 cd/m². APEX DISPLAY CO., LTD. 7

8 5 BLOCK DIAGRAM APEX DISPLAY CO., LTD. 8

9 6 PIN ASSIGNMENT 6-1 Pin Assignment Table Pin No. Symbol Type Function 1 NC --- No connection. 2 VSS I Ground pin 3 GDR O This is an output pin drives the external NMOS. 4 VDDB I This is a power supply pin 5 FB I This is a feedback resistor input pin. 6 RESE I This is a source current pin. 7 VBREF I This is an internal voltage reference pin 8 NC --- No connection. 9 NC --- No connection. 1 NC --- No connection. 11 VDD I Voltage supply pin (for logic) 12 BS1 I MCU interface selection pin 13 BS2 I MCU interface selection pin 14 NC --- No connection. 15 CS# I Chip select pin 16 RES# I Reset signal pin 17 D/C# I Data/Command control pin 18 R/W# I Read/Write selection pin 19 E I Enable signal pin 2~27 D~ D7 I/O 8-bit bi-directional data bus 28 IREF I This pin is segment output current reference pin 29 VCOMH O 3 VCC I OLED driving voltages 31 NC --- No connection. APEX DISPLAY CO., LTD. 9

10 6-2 Pin Description BS1, BS2 These are MCU interface input selection pins. See the following table for selecting different interfaces: 68-parallel interface 88-parallel interface Serial interface BS1 1 BS2 1 1 CS# This pin is the chip select input. The chip is enabled for MCU communication only when CS# had been pulled low. RES# This is a reset signal input pin. When it is pulled LOW, initialization of the chip is executed. D/C This is the Data/Command control pin. When it is pulled HIGH, the input at D7-D is treated as display data. When it is pulled LOW, the input at D7-D is transferred to the command registers. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams. R/W (WR#) This is a MCU interface input pin. When 68-series Parallel Interface mode is selected, this pin is used as Read/Write (R/W) selection input. Pull this pin to HIGH for read mode and pull it to LOW for write mode. When 88-series Parallel Interface mode is selected, this pin is used as Write (WR#) selection input. Pull this pin to LOW for write mode. Data write operation is initiated when this pin is pulled LOW and the CS# is pulled LOW. E (RD#) This is a MCU interface input pin. When 68-series Parallel Interface is selected, this pin is used as Enable (E) signal. Read/Write operation is initiated when this pin is pulled HIGH and the CS# pin is pulled LOW. When 88-series Parallel Interface is selected, this pin is used to receive the Read Data (RD#) signal. Data read operation is initiated when this pin is pulled LOW and CS# pin is pulled LOW. D7-D These are 8-bit bi-directional data bus to be connected to the microprocessor s data bus. When serial interface mode is selected, D1 will be the serial data input, SDIN, and D will be the serial clock input, SCLK. VDD This is a logic voltage supply pin. It must be connected to external source. APEX DISPLAY CO., LTD. 1

11 VSS This is a ground pin. It also acts as a reference for the logic pins and the OLED driving voltages. It must be connected to external ground. VCC This is the most positive voltage supply pin of the OLED panel. It should be supplied externally. IREF This is a segment current reference pin. A resistor should be connected between this pin and VSS. Set the current at 1uA. VCOMH This is an output pin for the voltage output high level for COM signals. A capacitor should be connected between this pin and VSS. NC Do not group or short NC pins together. VDDB This is a power supply pin for the internal buffer of the DC-DC voltage converter. It must be connected to VDD when the converter is used. GDR This is an output pin drives the gate of the external NMOS of the booster circuit. RESE This is a source current pin of the external NMOS of the booster circuit. VBREF This is an internal voltage reference pin for booster circuit. A stabilization capacitor, typ. 1uF, should be connected to Vss. FB This is a feedback resistor input pin for the booster circuit. It is used to adjust the booster output voltage level. APEX DISPLAY CO., LTD. 11

12 7 FUNCTION BLOCK DESCRIPTION 7.1 MPU Parallel 68/88-Series Interface Timing Characteristics Series MPU Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -4 to 85 C) Symbol Parameter Min Typ Max Unit tcycle Clock Cycle Time ns tas Address Setup Time - - ns t A H Address Hold Time - - ns tdsw Write Data Setup Time ns tdhw Write Data Hold Time ns tdhr Read Data Hold Time ns t O H Output Disable Time ns tacc Access Time ns PWCSL Chip Select Low Pulse Width (read) 12 Chip Select Low Pulse Width (write) 6 ns PWCSH Chip Select High Pulse Width (read) 6 Chip Select High Pulse Width (write) 6 ns tr Rise Time ns tf Fall Time ns APEX DISPLAY CO., LTD. 12

13 Series MPU Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -4 to 85 C) Symbol Parameter Min Typ Max Unit tcycle Clock Cycle Time ns tas Address Setup Time - - ns tah Address Hold Time - - ns tdsw Write Data Setup Time ns tdhw Write Data Hold Time ns tdhr Read Data Hold Time ns toh Output Disable Time ns tacc Access Time ns PWCSL PWCSH Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) tr Rise Time ns tf Fall Time ns ns ns APEX DISPLAY CO., LTD. 13

14 7.1.3 Serial Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -4 to 85 C) Symbol Parameter Min Typ Max Unit tcycle Clock Cycle Time ns tas Address Setup Time ns tah Address Hold Time ns tcss Chip Select Setup Time ns tcsh Chip Select Hold Time ns tdsw Write Data Setup Time ns tdhw Write Data Hold Time ns tclkl Clock Low Time ns tclkh Clock High Time ns tr Rise Time ns tf Fall Time ns APEX DISPLAY CO., LTD. 14

15 7.2 Graphic Display Data RAM(GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 x 64 bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display. 7.3 Current Control and Voltage Control This block is used to derive the incoming power sources into different levels of internal use voltage and current. VCC and VDD are external power supplies. VREF is reference voltage, which is used to derive the driving voltage for segments and commons. IREF is a reference current source for segment current drivers. 7.4 Segment Drivers / Common Drivers Segment drivers deliver 132 current sources to drive OLED panel. The driving current can be adjusted from to 3uA with 256 steps. Common drivers generate voltage scanning pulses. 7.5 Area Color Decoder Page and Page 1 of the display are divided into 32 banks. Bank16 and Bank32 comprise of a display area of 12 x 8 pixels. Other banks (~15 & 17~31) have matrices of 8 x 8 pixels. Each bank can be programmed to any one of the four colors (color A, B, C, D). Detailed operation can be referred to the Command Table. APEX DISPLAY CO., LTD. 15

16 7.6 DC-DC Voltage Converter It is a switching voltage generator circuit, designed for handheld applications. In SSD133, internal DC-DC voltage converter accompanying with an external application circuit (shown in below figure) can generate a high voltage supply VCC from a low voltage supply input VDD. VCC is the voltage supply to the OLED driver block. Below application circuit is an example for the input voltage of 3V VDD to generate VCC of ~ 2mA application. APEX DISPLAY CO., LTD. 16

17 Remark: 1. VSSB is tied to VSS on SSD133T3 package. 2. L1, D1, Q1, C5 should be grouped closed together on PCB layout. 3. R1, R2, C1, C4 should be grouped closed together on PCB layout. 4. The VCC output voltage level can be adjusted by R1and R2, the reference formula is: VCC = 1.2 x (R1+R2) / R2 The value of (R1+R2) should be between 5k to 1M Ohm. Components Typical Value Remark L1 Inductor, 1µH 1A D1 Schottky diode 1A, 25V Q1 MOSFET N-FET with low RDS(on) and low Vth voltage R1, R2 Resistor 1%,1/1W R3 Resistor, 1.2Ω 1%, 1/2W C1 Capacitor, 1µF 16V C2 Capacitor, 6.8µF Low ESR, 25V C3 Capacitor, 1µF 16V C4 Capacitor, 1nF 16V C5 Capacitor, 1 ~ 1 µf 16V C6 Capacitor,.1 ~ 1µF 16V C7 Capacitor, 15nF 16V 7.7 Reset Circuit When RES# pin is pulled LOW, the chip is initialized with the following status: 1. Display is OFF x 64 Display Mode 3. Normal segment and display data column address and row address mapping (SEG is mapped to column address H and COM is mapped to row address H) APEX DISPLAY CO., LTD. 17

18 4. Shift register data clear in serial interface 5. Display start line is set at display RAM address 6. Column address counter is set at 7. Normal scan direction of the COM outputs 8.Contrast control register is set at 8H 8 COMMAND FUNCTION 8.1 Configuration Command Table (D/C =, R/W (WR#)=, E (RD#)=1) D/C Hex D7 D6 D5 D4 D3 D2 D1 D Command Description ~F X3 X2 X1 X Set Lower Column Set the lower nibble of the column address register using X3X2X1Xas data bits. APEX DISPLAY CO., LTD. 18

19 1~1F 1 X3 X2 X1 X Address Set Higher Column Address The initial display line register is reset to b after POR. Set the higher nibble of the column address register using X3X2X1Xas data bits. The initial display line register is reset to b after POR A[2:] Set the number of column scroll per A[2:] * * * * * A2 A1 A B[2:] * * * * * B2 B1 B C[1:] * * * * * * C1 C Horizontal scroll setup step Valid value: 1b, 1b, 11b, 1b B[2:] Define start page address C[1:] Set time interval between each scroll step in terms of frame frequency b 12 frame 1b 64 frames 1b 128 frames 11b 256 frames D[2:] * * * * * D2 D1 D D[2:] Define end page address 2F E A[7:] A7 A6 A5 A4 A3 A2 A1 A Activate horizontal scroll Deactivate horizontal scroll Set Contrast Control Register ** Set the value of D[2:] larger or equal to B[2:] Start horizontal scrolling Stop horizontal scrolling Double byte command to select 1 out of 256 contrast steps. Contrast increases as the value increases. (POR = 8h) Set current drive pulse width of Bank, Color A, B and C. X[5:] * * X5 X4 X3 X2 X1 X Bank : X[5:] = 63; for pulse width set to 1 ~ 64 clocks A[5:] * * A5 A4 A3 A2 A1 A B[5:] * * B5 B4 B3 B2 B1 B C[5:] * * C5 C4 C3 C2 C1 C Set Look Up Table (LUT) for area color Color A: A[5:] same as above Color B: B[5:] same as above Color C: C[5:] same as above Note: color D pulse width is fixed at 64 clocks pulse. A[1:] :, 1, 1, or 11 for Color = A, B, C or D of bank 1 A[7:] A7 A6 A5 A4 A3 A2 A1 A A[3:2] :, 1, 1, or 11 for Color = A, B, Set bank color of for C or D of bank 2 B[7:] B7 B6 B5 B4 B3 B2 B1 B bank 1-16 (Page ) : : C[7:] C7 C6 C5 C4 C3 C2 C1 C D[7:6]:, 1, 1, or 11 for Color = A, B, D[7:] D7 D6 D5 D4 D3 D2 D1 D C or D of bank A[7:] A7 A6 A5 A4 A3 A2 A1 A B[7:] B7 B6 B5 B4 B3 B2 B1 B C[7:] C7 C6 C5 C4 C3 C2 C1 C D[7:] D7 D6 D5 D4 D3 D2 D1 D Set bank color of for bank (Page 1) A[1:] :, 1, 1, or 11 for Color = A, B, C or D of bank 17 A[3:2] :, 1, 1, or 11 for Color = A, B, C or D of bank 18 : : D[7:6]:, 1, 1, or 11 for Color = A, B, C or D of bank 32 APEX DISPLAY CO., LTD. 19

20 A~ A1 1 1 X A A6~A X A A[5:] * * A5 A4 A3 A2 A1 A AD X AE~AF X Set Segment Re-map Set EntON Display Set normal/ Inverse Display Set Multiplex Ratio Set DC-DC On/Off Set Display ON/OFF X=: column address is mapped to SEG (POR) X=1: column address 131 is mapped to SEG Entire display ON X=: normal display (POR) X=1: inverse display The next command, A[5:] determines multiplex ratio N from 16MUX-64MUX, POR= 64MUX X=1 DC-DC will be turned on when display on (POR) X= DC-DC is disable X=: turns OFF OLED panel (POR) X=1: turns ON OLED panel B~BF X3 X2 X1 X Set Page Address Set GDDRAM Page Address (~7) for read/write using X3X2X1X C/C8 1 1 X3 * * * Set COM Output Scan Direction X3=: normal mode (POR) Scan from COM to COM [N 1] X3=1: remapped mode. Scan from COM [N-1] to COM Where N is the Multiplex ratio. D A[5:] * * A5 A4 A3 A2 A1 A D Set Display Offset A[7:] A7 A6 A5 A4 A3 A2 A1 A Set Display Clock Divide Ratio/Oscillator Frequency Set vertical scroll by COM from -63. The value is reset to H after POR. The lower nibble of the next command define the divide ratio of the display clocks (DCLK): Divide ratio= A[3:] + 1, POR is b (divide ratio = 1) The higher nibble of the next command sets the Oscillator Frequency. Oscillator Frequency increases with the value of A[7:4] and vice versa. D8 /3 1 1 X5 1 X4 1 Set area color mode ON/OFF X5X4= (POR) : mono mode X5X4= 11 Area Color enable D A[7:] A7 A6 A5 A4 A3 A2 A1 A Set Pre-charge period A[3:] Phase 1 period of up to 15 dclk clocks [POR=2h] A[7:4] Phase 2 period of up to 15 dclk clocks [POR=2h] APEX DISPLAY CO., LTD. 2

21 Set COM pins hardware X4 1 configuration configuration X4=, Sequential COM pin configuration (i.e. COM31, 3, 29. ; SEG-132; COM31,32.62,63) X4=1(POR), Alternative COM pin (i.e. COM62,6,58, 2,; SEG-132; COM1,3,5 61,63) DB A[6:] low VCOM deselect level (~.43* Vref) Set VCOM Deselect A[6:] * A6 A5 A4 A3 A2 A1 A Level.77* Vref) (POR) 1111 normal VCOM deselect level high VCOM deselect level (equal* Vref) APEX DISPLAY CO., LTD. 21

22 8.2 Command Description Set Lower Column Address This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU. Set Higher Column Address This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU. Activate Horizontal Scroll Start motion of horizontal scrolling. This command should only be issued after Horizontal scroll setup parameters are defined. The following actions are prohibited after the horizontal scroll is activated 1. RAM access (Data write or read) 2. Changing horizontal scroll setup parameters The SSD133 horizontal scroll is designed for 128 columns scrolling only. 4 remaining columns are reserved for computation and should be left open. With column address mapped to SEG (Segment remap setting = Ah), the 4 unused columns will be SEG128, SEG129, SEG13, SEG131. With column address mapped to SEG131 (Segment remap setting = A1h), the 4 unused columns will be SEG, SEG1, SEG2, SEG3. Horizontal scroll direction Deactivate Horizontal Scroll Stop motion of horizontal scrolling. Horizontal Scroll Setup This command consists of 5 consecutive bytes to set up the horizontal scroll parameters. It determined the scrolling start page, end page and the scrolling speed. Before issuing this command, the horizontal scroll must be deactivated (2Eh). Otherwise, ram content may be corrupted. APEX DISPLAY CO., LTD. 22

23 Set Contrast Control Register This command is to set Contrast Setting of the display. The chip has 256 contrast steps from to FF. The segment output current increases as the contrast step value increases. Segment current vs Contrast setting Segment output current setting: Iseg =(Cr/256) * Iref * scale factor Where: Cr is contrast step Iref is reference current equals 1Ua Scale factor =32 Set Look Up Table (LUT) for area color SSD133 provides 4 color (pulse width) settings - Color A, B, C and D. The color intensity (or grey scale) is defined by the current drive pulse width. The pulse width of color A, B, C can be programmable from 1 to 64 DCLK* duration. The color D is fixed at 64 DCLK pulse width. This color setting has to be stored in the Look Up Table (LUT). For the background color, the color intensity is defined by a variable X[5:]. Set LUT command: 111 X[5:] A[5:] B[5:] C[5:] Description Number of DCLKs Bank Set background color X[5:] Color A Set Pulse Width A A[5:] Color B Set Pulse Width B B[5:] Color C Set Pulse Width C C[5:] Color D Pulse width D is fixed to 64 DCLK 64 (fixed) DCLK: Internal Display Clock APEX DISPLAY CO., LTD. 23

24 Set bank color of bank 1-16 (Page ) and bank color of bank (Page 1) Next step is to define the color of each display area. The 132x64 display matrix is divided into 8 pages of 8 commons per pages. The first two pages, page and page 1, are divided into 32 banks: Bank16 and Bank32 comprise of a display area of 12x8 pixels. Other banks (~15 & 17~31) have matrices of 8x8 pixels. Each bank can be programmable to any 1 of the 4 color (A, B, C, D). User can use 92h and 93h command for the bank color setting. Note: Only applicable in area color mode. Set Segment Re-map This command changes the mapping between the display data column address and segment driver. It allows flexibility in OLED module design. Refer to Command Table. Set Entire Display ON This command forces the entire display to be ON regardless of the contents of the display data RAM. This command has priority over normal/reverse display. Set Normal/Inverse Display This command sets the display to be either normal/inverse. In normal display, a RAM data of 1 indicates an ON pixel while in inverse display; a RAM data of indicates an ON pixel. Set Multiplex Ratio This command switches default 63 multiplex mode to any multiplex ratio from 2 to 63. The output pads COM-COM63 will be switched to corresponding COM signal. Set Display ON/OFF This command turns the display ON or OFF. When the display is OFF, the segment and common output are in high impedance state. Set Page Address This command positions the page address from to 7 in GDDRAM. Refer to Command Table. Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in OLED module design. In addition, the display will have immediate effect once this command is issued. That is, if this APEX DISPLAY CO., LTD. 24

25 command is sent during normal display, the graphic display will be vertically flipped. Set Display Offset This is a double byte command. The next command specifies the mapping of display start line to one of COM-63 (it is assumed that COM is the display start line, display start line register equals to ). For example, to move the COM16 towards the COM direction for 16 lines, the 6-bit data in the second byte should be given by 1. To move in the opposite direction by 16 lines, the 6-bit data should be given by (64 16) and so the second byte should be 1. Set Display Clock Divide Ratio/ Oscillator Frequency This command is used to set the frequency of the internal display clocks, DCLKs. It is defined as the divide ratio (Value from 1 to 16) used to divide the oscillator frequency. POR is 1. Frame frequency is determined by divide ratio, number of display clocks per row, MUX ratio and oscillator frequency. Set Area Color Mode ON/OFF This command is used to enable area color mode. POR is mono mode. Set Pre-charge period This command is used to set the duration of the pre-charge period. The interval is counted in number of DCLK. POR is 2 DCLK. Set COM pins hardware configuration This command is to set the COM signals pin configuration (sequential or alternative) to match the OLED panel hardware layout. Set VCOM deselect level This command is to set the COM pin output voltage level at deselect stage. APEX DISPLAY CO., LTD. 25

26 8.3 Application Circuit Serial BS1 1 BS2 1 1 Pin connected to MCU interface: D~D7, E, R/W#, D/C#, RES#, CS# C1~C3: 4.7uF Voltage at IREF = VCC 3V R1 = (Voltage at IREF - VSS) / IREF EX: VCC=12V, R1=(12-3)/1uA=9K APEX DISPLAY CO., LTD. 26

27 8.4 Pin Assignment APEX DISPLAY CO., LTD. 27

28 8.5 Software Flowchart APEX DISPLAY CO., LTD. 28

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30 9 RELIABILITY No. Parameter Conditions Quantit y 1 High Temperature (Operating) 7 C±2 C, 24hrs (all pixels 5 on) 2 Low Temperature (Operating) -2 C±2 C,24hrs (all pixels 5 ) Damp Proof Test 3 659%RH1,Ihrs(alapxels lo) n) 5 5 (High Temp/High Humi.) 4 Damp Proof Test (High Temp/High Humi.) (S ) 659,9%RH1,1hrs rs Heat Shock Test (Storage) -4 C (3min) 25 C (5min) 85 C (3min) 25 C (5min) 2 Note 1: Unless otherwise specified, tests will be not conducted under functioning state. Note 2: It should be checked at the actual driving condition under the high temperature. Note 3: No dew condensation to be observed. Note 4: The function test shall be conducted after 4 hours storage at the normal temperature and humidity after removed from the test chamber. Note 5: The function test is OK. Note 6:No addition to the defect. Luminance:>5% of initial value. 5 APEX DISPLAY CO., LTD. 3

31 1 INSPECTION STANDARDS 1.1 Sampling Method AQL : Major.65 ; Minor Inspection Condtion Test and measurement are performed under following conditions,unless otherwise specified. Temperature : 2 15 % Humidity : 65 2 %R.H. Pressure : 86~16hPa Distance between the panel and eyes of the inspector 3cm 1.3 Electrical Characteristics No Item Criterion AQL 1 Non operational No-Go Major 2 Luminance According to specification Major 3 CIE coordinates According to specification Major 4 Contrast irregularity Non detectable by the eye Major 5 Power consumption According to specification Major APEX DISPLAY CO., LTD. 31

32 1.4 Appearance Defect APEX DISPLAY CO., LTD. 32

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35 11 APPLYING PRECAUTIONS Please contact us when questions and/or new problems not specified in this specification arise. 12 PRECATIONS RELATING PRODUCT HANDLING The Following precautions will guide you in handling our product correctly. 1) Organic light emitting display (OLED) (1) The Organic light emitting display (OLED) panel used in the OLED module is made of plate glass. Avoid any strong mechanical shock. Should the glass break handle it with care. (2) The polarizer adhering to the surface of the OLED is made of a soft material. Guard against scratching it. 2) Care of the OLED module against static electricity discharge. (1) When working with the module, be sure to ground your body and any electrical equipment you may be using. We strongly recommend the use of anti static mats (made of rubber), to protect worktables against the hazards of electrical shock. (2) Avoid the use of work clothing made of synthetic fibers. We recommend cotton clothing or other conductivity-treated fibers. (3) Slowly and carefully remove the protective film from the OLED module, since this operation can generate static electricity. 3) When the OLED module alone must be stored for long periods of time: (1) Protect the modules from high temperature and humidity. (2) Keep the modules out of direct sunlight or direct exposure to ultraviolet rays. (3) Protect the modules from excessive external forces. 4) Use the module with a power supply that is equipped with an over current protector circuit, since the module is not provided with this protective feature. 5) Should hands or clothing come in contact with OLED powder, wash immediately with detergent. 6) Conductivity is not guaranteed for models that use metal holders where solder connections between the metal holder and the PCB are not used. Please contact us to discuss appropriate ways to assure conductivity. 7) Models which use flexible cable: (1) In order to maintain reliability, do not touch or hold by the connector area. (2) Avoid any bending, pulling, or other excessive force, which can result in broken connections. APEX DISPLAY CO., LTD. 35

36 13 WARRANTY This product has been manufactured to your company s specifications as a part for use in your company s general electronic products. It is guaranteed to perform according to delivery specifications. For any other use apart from general electronic equipment, we cannot take responsibility if the product is used in medical devices, nuclear power control equipment, aerospace equipment, fire and security systems, or any other applications in which there is a direct risk to human life and where extremely high levels of reliability are required. If the product is to be used in any of the above applications, we will need to enter into a separate product liability agreement. (1) We cannot accept responsibility for any defect, which may arise from additional manufacturing of the product (including disassembly and reassembly), after product delivery. (2) We cannot accept responsibility for any defect, which may arise after the application of strong external force to the product. (3) We cannot accept responsibility for any defect, which may arise due to the application of static electricity after the product has passed your company s acceptance inspection procedures. We cannot accept responsibility for industrial property, which may arise through the use of your product, with exception to those issues relating directly to the structure or method of manufacturing of our product. APEX DISPLAY CO., LTD. 36

37 14 OUTLINE DRAWING APEX DISPLAY CO., LTD. 37

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