PI3WVR31310A evaluation board User s manual By Paul Li. Table of Content
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1 PIWVR0A evaluation board User s manual By Paul Li Table of Content.0 Introduction.0 Quick start.0 Appendix A: the layout of PIWVR0A evaluation board.0 Appendix B: PIWVR0A evaluation boards schematic Page of
2 .0 Introduction The PIWVR0A evaluation board is to evaluate PIWVR0A for : DP DEMUX function..0 Quick start.. Connect the setup Plug EVB in DP source port (figure ) and connect EVB to DP monitors using m DP cables. Assure the.v on JP (with jumper) from DP source port. Otherwise using USB cable to provide V power from PC to J (USB port) on EVB. Figure, PIWVR0A evaluation board test setup Page of
3 Figure, PIWVR0A EVB function settings. Auto switching test Connect only one DP monitor to DP port-, port- or port- as in figure-. Set control-pins as in table-. The EVB will connect the DP monitor (in any port) to the DP source port Pin name Pin logic SW on-off Function CEB 0 CH on Activate the chip SEL[:0] CH off; CH off Auto switching DEMUX_MUX 0 CH on : DEMUX mode DP_HDMI 0 CH on DP mode PRI_SEL 0 (or, or M) CH off; CH on Priority: port- > port- > port- Table, PIWVR0A EVB settings for auto switching test Page of
4 . Priority test Connect (or ) DP monitors to any DP port-, port- or port- as in figure-. Set control-pins as in table-. The EVB will connect the DP monitor with higher priority. Pin name Pin logic SW on-off Function CEB 0 CH on Activate the chip SEL[:0] CH off; CH off Priority switching DEMUX_MUX 0 CH on : DEMUX mode DP_HDMI 0 CH on DP mode PRI_SEL 0 CH off; CH on Priority: port- > port- > port- PRI_SEL CH on; CH off Priority: port- > port- > port- PRI_SEL M (mid) CH on; CH on Priority: port- > port- > port- Table, PIWVR0A EVB settings for priority switching test. Manual switching test Connect, or DP monitors to DP port-, port- or port- as in figure-. Set control-pins as in table-. The EVB will connect the monitor manually selected by SEL[:0]. Pin name Pin logic SW on-off Function CEB 0 CH on Activate the chip SEL[:0] 00 CH on; CH on Port- is manually selected SEL[:0] 0 CH on; CH off Port- is manually selected SEL[:0] 0 CH off; CH on Port- is manually selected DEMUX_MUX 0 CH on : DEMUX mode DP_HDMI 0 CH on DP mode PRI_SEL NA NA Priority function disabled Table, PIWVR0A EVB settings for manual switching test Page of
5 .0 Appendix A: the layout of PIWVR0A evaluation board Note: No chokes needed when design PIWVR0A in any system. PIWVR0A is a passive switch without EMI issue. Chokes are needed for EMI problem seen with active drivers. Page of
6 .0 Appendix B: PIWVR0A evaluation boards schematic Note: No chokes needed when design PIWVR0A in any system. PIWVR0A is a passive switch without EMI issue. Chokes are needed for EMI problem seen with active drivers. Page of
7 .K.K.K.K.K M M R R R0 R R R R R R R SHLD SHLD M- M+ DP_HDM I AUXN AUXP CAB_ AUXN AUXP CAB_ SHELL SHELL /OE Vdd SEL M M 0 SHELL 00 DP_HDM I AUXN/SDA AUXP/SCL CAB_ AUXN/SDA AUXP/SCL CAB_ R R R0 R R SHLD SHLD R SHELL SHELL SHELL P D0P D0N DP DN DP DN DP DN PRI_SEL OEB M M 0 R R R R R SHLD SHLD u.u 00u u u C C C C C SHELL SHELL J P # _DP _DP J CON_USB.0_M inib_smt VBUS D- D+ ID C.u C + C +V C C U VIN EN VOUT NC PTM0 _USB D B00LW + C C C C C0 C C C D+A D-A D+A D-A D+A D-A CAB_ AUXP AUXN D0+A D0-A _DP C 0 0 J ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) U u CON_DP_Sourc e_recept Du al Mo de D P So urc e J ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) 0 ML_Lane (p) ML_Lane (n) 0 _DP CON_DP_Plug C U C R K SEL SEL0 CAB_ 0 0 D0P D0N DP DN DP DN DP DN SEL SEL0 _SRC CAB_SRC CAB_ DEM UX_MUX AUXP AUXN SCL SDA PIWV R0 D0P D0N DP DN DP DN DP DN D0P D0N DP DN DP DN DP DN AUXP/SCL AUXN/SDA 0 0 D0P D0N DP DN DP DN DP DN D0P D0N DP DN DP DN DP DN AUXP AUXN C0 C C C C C C C D0+B D0-B D+B D-B D+B D-B D+B D-B CAB_ AUXP AUXN _DP C0 0 0 J ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) u CON_DP_Sourc e_recept AUX+_SCL AUX-_SDA PIUSB0ZLE Y+ Y- D+ D- SCL SDA AUXP AUXN R R K/NP K/NP C C C C C C C C CAB_ AUXP AUXN D0+C D0-C D+C D-C D+C D-C D+C D-C _DP C 0 0 J ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) ML_Lane (p) ML_Lane (n) SW OEB SEL0 SEL DEM UX_MUX DP_HDM I PRI_SEL 0 SW_X_Half_Pitch R 0 R 0 R 0 R 0 R 0 R0.K R.K PIWVR0A evaluation board schematic u CON_DP_Sourc e_recept Title PIWVR0 HDMI : DEMO BOARD SCHEMATIC Size Document Number Rev A Date: Wednesday, June 0, 0 Sheet of Page of //0
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