JTAG (IEEE /P1149.4)

Transcription

1 and Boundary-Scan rchitecture Scan effectively partitions digital logic to facilitate control and observation of its function Chip-Internal Scan: Partitions chips at storage cells (latches/ flipflops) to effectively partition sequential logic into clusters of combinational logic Boundary-Scan: Partitions boards at chip I/Os for control and observation of board-level nodes (IEEE 49./P49.4) utorial Introductory L Sept ()-ut.I I est Symposium L Sept ()-ut.I- 997 I est Symposium he Incredible Shrinking Board Miniaturization results in loss of test access Standard pproach o est / IEEE 49. Yesterday oday om orrow? Developed by oint est ction roup (over 2 SC, test, and system vendors) starting in mid '8's Sanctioned by IEEE as Std 49. est ccess Port and Boundary-Scan rchitecture in 99 Solution: Build test facilities/test points into chips Focus: Ensure compatibility between all compliant ICs L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium he Ever-Expanding Chip Standard est ccess Port... Increasing integration at chip level complicates controllability User Register RS* Yesterday? C C D D oday 4/5-Wire Interface at Chip-Level Serial Instruction/Serial Data Port Extensible to Include user-defined instructions user-defined data registers L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

2 Conventional Methods of Board est In-Circuit est ( Bed-of-Nails est) Chip function can be ignored for shorts testing Chip function must be considered for continuity test est generation, though automated, requires IC models L Sept ()-ut.I I est Symposium Can t fford Not o est Cost will increase by a factor of ten as fault finding moves from one level of complexity to the next. he result: Reduced Profit Margins Delayed Product Introduction. Device level unit of cost 2. Board level units of cost 3. System level units of cost 4. Field level, units of cost Dissatisfied Customers L Sept ()-ut.I- 997 I est Symposium he Boundary Scan Idea In-Circuit test points moved onto the silicon, creating Virtual Nails Boundary scan cells bound each net, providing for continuity testing Observe/Control cells provide for test and normal function Conventional Methods of Board est Functional est ( Edge-Connector est) Based on board function, rather than structure est generation primarily manual est access limited to primary I/O only L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium he Boundary Scan Idea Scan provides a means to arbitrarily observe test results and source test stimulus Scan method requires minimal on chip/board resources (pins/nets) Conventional Methods of Board est In-Circuit est ( Bed-of-Nails est) Based on board structure, but limited by chip complexity Expensive testers and fixtures required est access limited by: Fine pitch packages Double-sided boards Conformal coating MCMs L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

3 he Control rchitecture Boundary Scan Method of Board est Boundary scan and other test data registers operate under control of instruction register Data is scanned from to through selected test data register or instruction register under control of est ccess Port () controller operates synchronously to using for state selection Based on board structure; Not limited by chip function/ complexity est access is not limited by board physical factors L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium (IEEE 49./P49.4) utorial - Intermediate he est Logic rchitecture he REQUED elements of the test logic architecture are: est ccess Port () One Set of Data Registers ll such elements are REQUED to be dedicated test logic (not used for any other purpose) with the exception of user-defined data registers Boundary Scan Method of Board est Chip function need not be considered for board test (shorted/open nets) est generation is highly automated; Simple In-Circuit Library models (BSDL) are vendorsupplied or ED-generated L Sept ()-ut.II I est Symposium L Sept ()-ut.I I est Symposium he est ccess Port (IEEE 49./P49.4) utorial - Intermediate he Boundary Scan Cell RS* User Register 4 wire interface REQUED either power-up reset or 5th wire, RS*, is REQUED all pins are REQUED to be dedicated (not used for any other purpose) pullups REQUED at and (also, RS*, if implemented) all inputs (e.g., ) are REQUED to be sampled on rising, all outputs (e.g. ) are REQUED to be propagated on falling NI (Normal Input) SO (Serial Output) OBSERVE CONROL ES/D MUX CPURE/SCN MUX SCN UPDE LCH/FLOP LCH/FLOP SI (Serial Input) NO (Normal Output) L Sept ()-ut.II I est Symposium L Sept ()-ut.I I est Symposium

4 (IEEE 49./P49.4) utorial - Intermediate he UPDE RESE SHIF CLOCK Shadow Latches Shift Register he instruction register is REQUED to be at least 2 bits in length he instruction register is REQUED to capture the binary value in its 2 least-significant bits on the rising edge of in Capture- (other bits may capture user-specified data) he instruction register is REQUED to have a latched parallel output such that a new instruction only takes effect after shifting is complete (on falling edge of in Update-) he instruction register is REQUED to reset to Idcode (if implemented), otherwise to Bypass L Sept ()-ut.II I est Symposium X.. est Logic Reset Run est/idle Select -Scan state transitions occur on rising edge of based on the current state and the input value ONLY he Capture Shift- Exit - Pause- Exit 2- Update- (IEEE 49./P49.4) utorial - Intermediate Select -Scan Capture- Shift- Exit - Pause- Exit 2- Update- L Sept ()-ut.II I est Symposium he controller is REQUED to conform exactly to this state diagram he instruction scan sequence is REQUED to access only the single instruction register he data scan sequence is REQUED to access only the data register selected by the current instruction is REQUED to be active only in the Shift- and Shift- states (IEEE 49./P49.4) utorial - Intermediate he est Data Registers (IEEE 49./P49.4) utorial - Intermediate he Outputs device id Only 2 test data registers are REQUED: he boundary-scan register - the serial concatenation of all boundary-scan cells, at least one for each digital signal pin he bypass register hese registers, and the device identification register, if implemented, are REQUED to be dedicated test logic (used for no other purpose) RS* CLOCK UPDE SHIF RESE SHIF UPDE CLOCK SELEC EN Data Registers scan and update clocks and shift/capture select scan and update clocks and shift/capture select enable and instruction/data select L Sept ()-ut.II- 997 I est Symposium L Sept ()-ut.II I est Symposium he Boundary-Scan Register (IEEE 49./P49.4) utorial - Intermediate he boundary-scan register is REQUED to be a concatenation of all boundary-scan cells it is REQUED that there be at least one BSC for each digital input or output to the system logic (including on-chip outputs to analog circuitry) it is REQUED that there NO be BSCs at» pins» compliance enables» non-digital signals Register (REQUED/ Optional) Register Summary (IEEE 49./P49.4) utorial - Intermediate Length Capture Value Selected by Instruction(s) INSRUCION at least two X.. n/a BOUNY user-specified user-specified Extest Sample/Preload Intest Clamp HighZ BYPSS exactly one Bypass Device ID exactly 32 X.. Idcode Usercode user-defined user-specified user-specified user-specified L Sept ()-ut.II- 997 I est Symposium L Sept ()-ut.II I est Symposium

5 he Extest Instruction (REQUED) Provides for test external to chip, such as interconnect test Output pins operate in test mode, driven from contents of BSC update latch Input data captured in BSC scan latches prior to shift operation Shift operation allows test response to be observed at while next test stimulus inserted at Following shift operation, new test stimulus transferred to BSC update latches he (IEEE 49./P49.4) utorial - Intermediate he bypass register is REQUED to be one bit in length he bypass register is REQUED to capture a logic value in Capture- state It is REQUED that any operation of the bypass register have no effect on the operation of the system logic L Sept ()-ut.I I est Symposium L Sept ()-ut.II I est Symposium he Sample/Preload Instruction (REQUED) Provides means to preload boundary before entry to test mode Output and input pins operate in normal mode Input pin data and core logic output data captured in BSC scan latches Shift operation allows test response to be observed while next test stimulus inserted at Following shift operation, new stimulus transferred to BSC update latches L Sept ()-ut.I I est Symposium (IEEE 49./P49.4) utorial - Intermediate he Device Identification Register 4 bits 6 bits bits Ver Part Code device id Mfr Code he device identification register is REQUED to be a 32-bit register It is REQUED to capture a device-specific value in Capture- state - this value has 4 fields LSB = always logic - = mfr code 2-27 = part code 28-3 = version code It is REQUED that any operation of the device identification register have no effect on the operation of the system logic L Sept ()-ut.II I est Symposium Note: For I components, the mfr code + LSB will always have value 2F lso, I contact for part codes is Doug Kostlan, d-kostlan@ti.com. Version codes are managed by the originating product group. he Bypass Instruction (REQUED) Instruction Summary (IEEE 49./P49.4) utorial - Intermediate Provides for abbreviated scan path through chip Output and input pins operate in normal mode he one-bit bypass register is selected for scans Mandatory that an all-ones value updated into the decodes to Bypass, as well as any opcodes which are otherwise undefined Instruction (REQUED/ Optional) Opcode Mode Selected Data Register EXES..* est Boundary SMPLE/PRELOD user-specified Normal Boundary BYPSS.. Normal Bypass Intest user-specified est Boundary Runbist user-specified est User-specified Idcode user-specified Normal Device ID Usercode user-specified Normal Device ID Clamp user-specified est Bypass HighZ user-specified est Bypass user-defined user-specified user-specified user-specified * revision in progress will remove the requirement for EXES opcode of all zero L Sept ()-ut.I I est Symposium L Sept ()-ut.II I est Symposium

6 Microprocessor LV852 Parallel Data In Logic Cluster est LV852 LV852 Control Logic (Non-Scan) Scan Path IEEE 49. Latch Registered ransceiver B852 B852 LV854 ddress Control Data Memory rray Interconnect est Full B/S Board ll nets bound by BSC's and/or primary I/O requiring no physical access Parallel access reduced to card edge only est generation and application fast and easy L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium Latch Memory est Interconnect est Partial B/S Board B852 B852 Registered ransceiver LV854 ddress Control Data Memory rray Memory array bound by boundary scan chips utomatic test patterns can be generated and driven from B/S outputs est response can be captured at B/S inputs ransceivers can test for net shorts w/o memory R/W BIS methods (PRP/PS) can be used for increased test throughput Not all nets are bound by boundary scan and/or primary I/O, perhaps requiring some IC access Expense and complexity reduced for test generation and test application for chips/nets with B/S access Cluster testing may be used to access non-scan nets L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium B B2 B3 B4 2B 2B2 2B3 2B4 D SN74BC SN74BC8244 Y Y2 Y3 Y4 2Y 2Y2 2Y3 2Y4 Memory est 256 x 8 RM rray D D D2 D3 D4 D5 D6 D7 WE CS MODE IEEE 49. EXES & SMPLE) IEEE 49. (with BIS capability) ime o pply Scans Patterns ime o pply Scans Patterns Y Y2 Y3 Y4 2Y 2Y2 2Y3 2Y4 SN74BC CCESSES Seconds Seconds 7 52,, CCESSES 375. Minutes 2,, 2,, <. Minutes 28, 2,, LOIC "CLUSER" Logic Cluster est Random-logic cluster is bound by boundaryscannable chips Deterministic test stimulus (P-generated) can be driven to cluster from B/S outputs est response can be captured at B/S inputs BIS methods (PRP/PS) can be used for increased test throughput and near "t-speed" performance L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

7 Manufacturing est System-Level est IC Provides test and diagnostic capabilities of in-circuit test without need/expense of physical access Improved fault coverage/diagnostic without large capital expense Highly automated test generation reduces test development time S P S P S P -addressable interface unit extends access beyond board-level System-level test System design verification Sys integration (Mfg test) Sys self-test (Field Svc) Supports in place board test and board-to-board test llows reuse of device/ board test data SP-ddressable Scan Port Device L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium System Configuration Maintenance Real pplications of the Provides low-level test access within configured systems for: In-house system integration Fielded-system test and diagnostics Built-in self-test In-field upgradability via ISP, etc. Remote field test, diagnostic and upgrade I N E R N L S C N E S BIS Emulation Programming Scan access to chips, boards, systems for: Design verification/debug Manufacturing test Hardware/software integration Field test/diagnostics ccess built-in self-test (BIS) ccess on-chip/in-circuit emulation (ONCE/ICE) ccess in-system programming (ISP) of PLDs/EEPROMs Let your imagination run wild!!! L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium IEEE Standards Call (8) 678-IEEE to ORDER Design Verification/Debug IEEE Std (Includes IEEE Std 49.a-993), IEEE Standard est ccess Port and Boundary-Scan rchitecture, ISBN , IEEE order number SH6626. he official document which specifies the international standard for a test access port and boundary-scan architecture. Informally known as the standard, it was officially ratified by the IEEE in February 99. Since, it has been supplemented twice. he first supplement, ratified in une 993, is included in the referenced document. he second supplement is currently a separate document, as referenced below. IEEE Std 49.b-994, Supplement to IEEE Std , ISBN , IEEE order number SH he official document which specifies the international standard for a boundary-scan description language. his supplement to IEEE Std was ratified in September 994. Provides control and observation of system under test without need for physical access Ease of set-up for test Can be used in standard system configuration (no need for card extenders, etc.) Can be used in environmental chambers Can access on-chip emulation for software/debug Can access ISP for code download/offload/ changes L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

8 utorials/handbooks he est ccess Port and Boundary-Scan rchitecture, Colin M. Maunder, Rodham E. ulloss, ed., IEEE CS Press, ISBN Edited by two principal chairs of the IEEE 49. working group, this Computer Society tutorial compiles several of the seminal papers on boundaryscan along with several invited papers on various topics including applications, implementation, and others. It will primarily be of interest to the design and/or test engineer. he Boundary-Scan Handbook, Kenneth P. Parker, Kluwer cademic Publishers, ISBN uthored by the principal force behind the Boundary-Scan Description Language (BSDL) and an IEEE 49. working group principal as well as a long time manufacturing and design-for-test expert, this is truly considered HE indispensable handbook on boundary scan for the design and/or test engineer. Boundary-Scan est - Practical pproach, Harry Bleeker, Peter van den Eijnden, Frans de ong, Kluwer cademic Publishers, ISBN uthored by several and IEEE 49. working group principals, this book is a ready reference to boundary-scan technology, its benefits, and considerations for design and test managers and engineers. L Sept ()-ut.I I est Symposium SIC SP E P BIS B/S BSC BSDL BSR BS CE DF DSP ED ebc FP HSDL ICE IC bbreviations/cronyms pplication-specific Integrated Circuit ddressable Scan Port utomatic est Equipment utomatic est Pattern eneration Built-In Self-est Boundary-Scan Boundary-Scan Cell Boundary-Scan Description Language Boundary-Scan Register Boundary-Scan est Computer-ided Engineering Design-for-est Data Register Digital Signal Processing/Processor Electronic Design utomation Embedded est Bus Field-Programmable ate rray Hierarchical Scan Description Language In-Circuit Emulation In-Circuit est L Sept ()-ut.I I est Symposium IEEE ISP MCM Mfg PCB PLD PRP PS PWB SPL SVF BC RS UU Institute of Electrical & Electronics Engineers In-System Programming oint est ction roup Multi-Chip Module Manufacturing Printed Circuit Board Programmable Logic Device Pseudo-Random Pattern eneration Parallel Signature nalysis Printed Wiring Board Scan Path Linker Serial Vector Format est ccess Port est Bus est Clock est Data Input est Data Output est Mode Select est Reset Unit Under est