Memory Arrays. Array Architecture. Chapter 16 Memory Circuits and Chapter 12 Array Subsystems from CMOS VLSI Design by Weste and Harris, 4 th Edition

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1 Chapter 6 Memory Circuits and Chapter rray Subsystems from CMOS VLSI Design by Weste and Harris, th Edition E E 80 Introduction to nalog and Digital VLSI Paul M. Furth New Mexico State University Static RM (SRM) Mask ROM Read/Write Memory (RM) (Volatile) Memory rrays Memory rrays Random ccess Memory Serial ccess Memory Content ddressable Memory (CM) Dynamic RM (DRM) Programmable ROM (PROM) Read Only Memory (ROM) (Nonvolatile) Erasable Programmable ROM (EPROM) Serial In Parallel Out (SIPO) Shift Registers Parallel In Serial Out (PISO) Electrically Erasable Programmable ROM (EEPROM) Queues Flash ROM First In First Out (FIFO) Last In First Out (LIFO) Random ccess Memory (RM) any can be accessed at any time row/ line selected first entire row of array selected column address chooses particular memory location Read or write operation on one at a time. External inputs rray rchitecture n s of m s each If n >> m, fold by k into fewer rows of more columns Good regularity easy to design Very high density if good cells are used 3

2 DRM (Dynamic RM) Cell One transistor, one capacitor. Most dense RM Requires refresh every ms or else voltage on C m will leak away (through off transistor). Refresh of stored or 0 occurs during a read operation, a whole row at a time. DRM using trench capacitor with shared line contact (to reduce column capacitance) 5 6 Three layers of poly required Poly for lines Poly/poly3 for capacitance 6T SRM Cell Cell size accounts for most of array size _b Reduce cell size at expense of complexity 6T SRM Cell Used in most commercial chips Data stored in crosscoupled inverters Read: Precharge, _b to V DD Raise line OR _b driven to 0 Write: Drive data onto, _b Raise line One side has a strong 0 written to it 7 8

3 SRM Read Precharge both lines high Turn on line One of the lines will be pulled down by cell Ex: = 0, _b = discharges, _b stays high But bumps up slightly Read stability must not flip N ~ x strength of N N, N weak _b P P N N _b N N3 _b _b time (ps) 9 SRM Write Drive one line high, the other low Turnon line Bitlines overpower cell with new value Ex: = 0, _b =, =, _b = 0 Force _b low, then rises high Writability Must overpower feedback inverter N >> P P, P weaker still N _b _b P N time (ps) P N3 _b _b N 0 SRM Sizing High lines must not overpower inverters during reads But low lines must write new value into cell Substrate contacts often placed outside cell _b Read _q Bitline Conditioning More Cells SRM Cell Very Strong Transistors Write _vf _b_vf H H med weak 8 strong med _b 8 _q, _b out_b_vr out_vr out_b, out 3

4 SRM Layout Cell size is critical: 6 x 5 (cells in industry much smaller!) Tile cells sharing V DD, GND, wires and line contacts Every 6 cells, tie straps, add substrate/well contacts POLY WORD (horizontal) M VDD (horizontal) M BIT/BIT_B, GND (vertical) M3 VDD, WORD (for strapping) M GND (for strapping) 0 ddress Decoders n: n decoder consists of n n-input ND gates One needed for each row of memory, driving x m nmos transistors, since m s in each row. Build ND from NND or NOR gates VDD GND BIT BIT_B GND 0 Static CMOS ND WORD Cell boundary 3 Large Decoders For n > 3, NND becomes slow Break large gates into smaller gates For n >, NOR becomes slow Z B C D B C D B C D 3 0 -input NND -input NOR Row line driver uses V DDP =.5V to turn on pass transistors in SRM cell better If row line driver is driven by -V inverter When output of -V inverter high Row driver NFET ON Row driver PFET not turned all the way OFF Drives NMOS Pass Transistors 5 6

5 Level Shifter Column Circuitry DEC signal goes from 0V to V Inverter powered using V If DEC = V M ON and M OFF M ON and M3 OFF row line =.5 V Motivation for sense amplifiers: large C col Circuitry required for each column Bitline conditioning Sense amplifiers Column multiplexing 7 8 Bit (column) line capacitance makes sensing (reading) SRM slow. Suppose line is 00 mx0. m ssume diffusion contact C n+/p- ~ 0.5 ff C m-to-sub = 0.03 ff/ m x ff/ m x P = 7fF C col = (number of lines/ shared) x C n+/p- + C m-to-sub For 56 lines, C col = 9 ff Sensing basics One (row) line is selected small SRM cell element in each column ( line) drives the large line capacitance Results in small change, e.g., V = 50 mv 9 0 5

6 Bitline Conditioning Precharge lines high before reads Equalize lines to minimize voltage difference when using sense amplifiers _b Very strong transistors to drive large -line capacitance. Clocked Sense mp Clocked sense amp saves power Requires sense_clk after enough line swing (delayed ) Isolation transistors cut off large line capacitance _b sense_clk 6 sense 6 / 8 / 6 sense_b isolation transistors regenerative feedback with L = L min Column Multiplexing Recall that array may be folded for good aspect ratio (more columns than rows) For example, k x 6s = 3ks gets folded into 8 rows x 56 columns = 3ks Must select 6 output s from the 56 columns Requires sixteen 6: column multiplexers Same circuit as in previous slide In+ =, In- = _b Out+ = sense, Out- = sense_b clock = sense_clk 3 9: SRM 6

7 Single Pass- Gate Mux SRM Block Diagram [5:0] 6 x 6 SRM rray Decoder and single pass transistor L Inverter means Low switching point (V SP ) made with large NMOS 5 symbol rsel[3:0] din write csel[3:0] rs[3:0] RowSel Buffers Input Gating ColSel Buffers rs[3:0] sclk [5:0] wdat0 wdat cs[3:0] cs[3:0] [5:0] [5:0] Pre-Charge Sense-mp [5:0] sens[5:0] Write Logic Column MUX col[5:0] Column Decoder sens[5:0] out out Output Buffer dout 6 ROM (Read-only memory) Most dense One transistor per memory Not writable after manufacturing (or burning ) 7 8 7