Glossary. ATPG -Automatic Test Pattern Generation. BIST- Built-In Self Test CBA- Cell Based Array

Transcription

1 Glossary ATPG -Automatic Test Pattern Generation BFM - Bus Functional Model BIST- Built-In Self Test CBA- Cell Based Array FSM - Finite State Machine HDL- Hardware Description Language ISA (ISS) - Instruction Set Architecture (Instruction Set Simulator); used interchangeably for an instruction set executable model of a processor LMG - Logic Modeling Group RTL - Register Transfer Level SoC - System-on-a-Chip SWIFT- Software Interface Technology VFM - Verilog Foundary Model VMC - Verilog Model Compiler VSIA- Virtual Socket Interface Alliance; homepage

2 Bibliography Books on software reuse: 1. Measuring Software Reuse, JeffreyS. Poulin, Addison Wesley, Practical Software Reuse, Donald J. Reifer, Wiley, Formal specification and verification: 1. the VSPEC homepage. 2. Formal Specification and Verification of Digital Systems, George Milne, McGraw-Hill, Formal Hardware Verification, Thomas Kropf (ed.), Springer, Management processes: 1. a description of the UltraSPARC project, mentioning construct by correction. 2. Winning the New Product Development Battle, Aoyd, Levy, Wolfman, IEEE. Books and articles on manufacturing test: 1. "Testability on Tap," Colin Maunder et al, IEEE Spectrum, February 1992, pp "Aiding Testability also aids Testing," Richard Quinell, EDN, August 12, 1990, pp "ASIC Testing Upgraded," Marc Levitt, IEEE Spectrum, May 1992, pp Synopsys Test Compiler User's Guide, v3.3a, Synopsys Test Compiler Reference Manual, v3.2, 1994.

3 218 Reuse Methodology Manual 6. Synopsys Certified Test Vector Formats Reference Manual. 7. Digital Systems Testing and Testable Design, M. Abromovici et al, Computer Science Press, The Boundary-Scan Handbook, Kenneth Parker, Kluwer Academic Publishers, The Theory and Practice of Boundary Scan, R. G. "Ben" Bennetts, IEEE Computer Society Press. 10. Testability Concepts for Digital /Cs, Franz Beenker et al, Philips Corp, "A Comparison of Defect Models for Fault Location with IDDQ Measurements," Robert Aitken, IEEE Design & Test, June 1995, pp Books and articles on synthesis: 1. "Rattening and Structuring: A Look at Optimization Strategies,'' Synopsys Application Note Version 3.4a, April1996, pp. 2-1 to VHDL Compiler Reference Manual, Synopsys Documentation Version 3.4a, April 1996, Appendix C. 3. DesignTime Reference Manual, Synopsys Documentation Version 3.4a, April "Commands, Attributes, and Variables,'' Synopsys Documentation Version 3.4a, April1996.

4 Index Symbols 'define statements (Verilog) 65 A Accelerated Verification System coding guidelines 204 process 201 active low signals 51 algorithmic model 15, 36 all_registers 106 application testing 122 architecture (VHDL) 53, 59 arrays 61 aspect ratio 144 asynchronous design style 20 logic 93 memory interface 98 reset 22 ATPG 30, 35, 107 B behavioral model 36 BIST logic 27, 143 RAM 26 block definition 3 system interconnect 23 block constructs (VHDL) 67 block diagram 34 blocking assignments (Verilog) 80 Bones 15 boundary scan 143 branch coverage 132 bug tracking 207 bus functional model 127, 129, 155 bus monitor 127 buses naming convention 51 on-chip 23, 25, 63 three-state 63 c CIC++ 36 case statements 83 CBA 162 CBA Transport 163 characterize-compile 1 04 check_design 107 check_test 107 clock buffers 25, 69 coding guidelines 67 distribution 25 domains 21 frequencies 21 gating 69, 70 hard macro 144 internal generation 70 mixed edges 67 naming convention 50 synthesis 105

5 220 Reuse Methodology Manual tree 25 code profiling 100 coding guidelines Accelerated Verification 204 basic 50 clock and reset 67 exceptions 172 functions 60 HDL translation 66 labels 62 loops and arrays 61 memory 98 partitioning 89 portability 63 readability 55 state machine 85 synthesis 73 synthesis scripts 116 testbench 134 combinational blocks 79 feedback 77 logic partitioning 90 loops 106 paths 103 comments, in source files 55 compare_design 47 compiled simulation 197 compliance tests 122 condition coverage 132 configuration (VHDL) 59 constants 64 construct by correction 13 core 3 corner tests 122 COSSAP 15, 37 coverage analyzing 132 branch 132 condition 132 macro testbench 132 path 132 statement 132 subblock testbench 124 toggle 133 trigger 133 cycle-based simulation 198 D data management design archive 208 multi-site 208 revision control 206 datapath design issues I 09 design methodologies 109 design tools 110 generators 110 datapath generators 178 debug strategy selection 24 structures 24 deliverables hard macro 168 soft macro 166 design archive 170, 208 design for reuse coding guidelines 50 general guidelines 5 requirements 5 design methodology bottom-up II spiral model 9 System-on-a-Chip 8 top-down ll waterfall model 9 design process hard macro 145 subblock 38 System-on-a-Chip 15 top-level macro 36 design reuse common problems 6 definition I implementing 2ll in System-on-a-Chip design 2 of legacy designs 212 design reviews 209 Design Ware 65 DFfAdvisor 43 documentation 44 hard macro 151 requirements 171 soft macro 47 E emulation in system-level verification 198 limitations 200 model 158 pros and cons 123 entity (VHDL) 59 event-based simulation 123, 197 executable specification 15

6 Reuse Methodology Manual 221 F false paths 96 FastScan 43 finn macro 4 FISPbus 24 FlexTest 43 Floorplan Manager 108 floorplanning feedback to synthesis I 07 hard macro 24 specification 25 floorplanning model 159 formal specification 14 formal verification 47, 196 hard macro 149 Formality 47, 107, 196 FPGA prototype 192 full functional model 155 full scan 143 function definitions 64 functional model 152 functional specification 30, 40, 209 G gates, instantiating 66, 96 generate statements (VHDL) 66 GTECH library 66 H hard macro aspect ratio 144 behavioral model 36 bus functional model 155 clock implementation 144 definition 4 deliverables 168 design for test 142 design process 145 designing with 177 development issues 141 documentation 151 emulation model 158 floorplanning 24 floorplanning model 159 full functional model 155 functional model 152 hardware model 158 integrating into SoC 176 models 151 physical design 149 pin placement 144 porosity 144 porting 162 power distribution 145 productization 149 reset implementation 144 selection 176 subblock integration 147 timing model 159 verification 149 hard-coded numerics 64, 116 hard-coded paths 116 hardware accelerator 198 hardware model 158 hardware modeler 123 hardware specification 14 hardware/software cosimulation 15, 203 partitioning 16 HDL translation 46, 57, 63 header, in source files 53 if-then-else statements 83 in-place optimization 181 interconnect on-chip blocks 23 subblocks 41 interpreted simulation 123, 197 ISA model 152 J JTAG 35 L labels 62 latches avoiding 75 checking for 75, 106 design issues 20 layout 107 limited production 125 Links-to-Layout 108 lint 40, 44, I 06 loops 61 LPGA prototype 192 M macro definition 3 design process 30 integration 41 partitioning 30 productization 30 See also hard macro

7 222 Reuse Methodology Manual See also soft macro specification 30 synthesis strategy 104 testbench design 127 timing budget I 02 top-level partitioning 35 top-level RTL 43 verification 124 manufacturing test documenting strategy 35 on-chip structures 26 strategy selection 26 Matlab 15 memory BIST 26 coding guidelines 98 design issues 108 test methodology 26 microprocessor ISA model 152 test strategy 27 Module Compiler 40, 112 multibit signals 51 multicycle paths 95 multiplexers 83 N naming conventions 50 nonblocking assignments (Verilog) 80 NuThena 15 p packages (VHDL) 64 parameter assigning values 64 mapping 58 naming convention 50 partitioning asynchronous logic 93 chip-level 97 combinational logic 90 critical path logic 91 macro into subblocks 30, 35 testbench 134 path coverage 132 phase locked loop 22 physical design hard macro 149 issues 24 of SOC with macros 179 PI-Bus 24 pin placement 144 place-and-route 107 point-to-point exceptions 95 porosity 144 port grouping 57 mapping 58 naming convention 51 ordering 57 power analysis 41, 44 Power Compiler 41, 44 power distribution 145 product development lifecycle 209 productization hard macro 149 soft macro 44 project plan 209 prototype 46, 123, 125 Q QuickPower 41,44 R RAM generators 114, 178 random tests 122 rapid prototyping 125 registers for output signals 89 inferring 73 regression tests 206, 207 report_timing 106 reserved words 57 reset asynchronous 22 coding guidelines 67 conditional 72 hard macro 144 internal generation 72 modeling in testbench 135 naming convention 51 strategy 22 synchronous 22 synthesis 105 resource sharing 93 revision control always-broken model 206 always-working model 206 implementing 206 requirement 44, 116, 170 routing channels 144 s scaninsertion 30,35,43 SDT 15 sensitivity list 78

8 Reuse Methodology Manual 223 sequential blocks 80 set_driving_cell 104 set_load 104 signal naming convention 52 registering outputs 89 signal assignments (VHDL) 82 silicon prototype 193 simulation code profiling 100 compiled 197 cycle-based 198 event-based 123, 197 gate-level 46, 138 interpreted 123, 197 simulator compatibility 63 macro portability 46 soft macro definition 4 deliverables 166 designing with 175 documentation 47 formal verification 47 gate-level simulation 46 installation 175 integrating into SoC 174 productization 44 selection 174 synthesis challenges 101 verification challenges 119 software model 35 requirements 35 specification 14 specification block 16 contents 34 executable 15 formal 14 functional 30, 40, 209 hardware 14 importance of 13 macro 30 requirements 14 software 14 subblock 30 system 15 technical 40 spiral model 9 SPW 15,37 state machine coding 85 statement coverage 132 static timing analysis 138, 149 std_logic 63 std_logic_ vector 63 std_ulogic 63 std_ulogic_ vector 63 subblock definition 4 design process 38 functional specification 40 integration 30 RTL coding 40 specification 30 synthesis strategy 104 technical specification 40 testbench coverage 124 testbench design 126 testbench requirements 40 timing budget 103 verification 124 subtypes (VHDL) 64 SWIFI' interface 36 synchronous design style 20 memory interface 98 reset 22 synthesis clock network 105 code checking after 106 code checking before 106 coding guidelines 73 early in design 104 guidelines 102 interactivity with layout 107 partitioning for 89 reset network 105 strategy selection 23, 102 top-level macro 43 synthesis scripts embedded 65 guidelines 116 subblock 40 top-level 43 system verification application-based verification 188 emulation 193 fast prototyping 191 formal verification 196 gate-level simulation 196 gate-level verification 194 hardware/software cosimulation 203 in-circuit testing 203 RTL acceleration 202 simulator selection 197 specialized hardware 198 strategy 184

9 224 Reuse Methodology Manual test plan 184 verifying behavior and data 186 verifying macro interfaces 185 verifying macro transactions 185 System-on-a-Chip design challenges 2 design flow diagram 12 design methodology 8 verification. See system verification T technical specification 40 technology CBA 162 independence 63,65 macro portability 46 Test Compiler 43 test insertion 44 testability checking for 107 coding for 73 gated clocks 69 test bench coding guidelines 134 coverage 41, 132 macro 30,36 output checking 127 partitioning 134 reset modeling 135 stimulus generation 126, 136 subblock 30,40,124 testbench design macro 127 subblock 126 TestGen 43 tiling 108 timing budget macro 102 subblock 103 timing model 159 timing verification 13 8 toggle coverage 133 translation, HDL 46 trigger coverage 133 types (VHDL) 63 u user guide 171 v variable assignments (VHDL) 82 verification application testing 122 compliance tests 122 comer tests 122 hard macro 149 macro 119, 124 of physical design 181 plan 121 random tests 122 strategy selection 26, 122 subblock 124 system-level. See system verification timing 138 tools 26, 123 Verilint 40, 106 VeriSure 41, 124 VHDLCover 41, 124, 132 VHDLlint 40, 106 virtual component 4 VITAL 52 VSIA 4 VSPEC 14 w waterfall model 9 wireload models 105